Part Number Hot Search : 
MICON 973506 1N957C MAX3012 HER102SG SD103 MA4K5 F3710ZS
Product Description
Full Text Search
 

To Download LFXP10E-4F484C Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  latticexp family handbook hb1001 version 02.9, april 2007
april 2007 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 1 section i. latticexp family data sheet introduction features ....................................................................................................................... ...................................... 1-1 introduction ................................................................................................................... ..................................... 1-2 architecture architecture overview .......................................................................................................... .............................. 2-1 pfu and pff blocks............................................................................................................. .................... 2-2 slice .......................................................................................................................... ................................ 2-3 routing........................................................................................................................ .............................. 2-6 clock distribution network ..................................................................................................... ............................ 2-6 primary clock sources.......................................................................................................... .................... 2-6 secondary clock sources........................................................................................................ ................. 2-7 clock routing.................................................................................................................. .......................... 2-8 sysclock phase locked loops (plls) ............................................................................................. ..... 2-9 dynamic clock select (dcs) ..................................................................................................... ...................... 2-11 sysmem memory .................................................................................................................. ........................... 2-11 sysmem memory block............................................................................................................ ............... 2-11 bus size matching .............................................................................................................. .................... 2-12 ram initialization and rom operation ........................................................................................... ........ 2-12 memory cascading ............................................................................................................... .................. 2-12 single, dual and pseudo-dual port modes........................................................................................ ..... 2-12 memory core reset .............................................................................................................. .................. 2-14 programmable i/o cells (pics).................................................................................................. ...................... 2-15 pio ............................................................................................................................ .............................. 2-16 ddr memory support............................................................................................................. ......................... 2-20 dll calibrated dqs delay block ................................................................................................. .......... 2-20 polarity control logic ......................................................................................................... ..................... 2-22 sysio buffer ................................................................................................................... .................................. 2-22 hot socketing.................................................................................................................. ........................ 2-25 sleep mode ..................................................................................................................... ................................. 2-25 sleepn pin characteristics ..................................................................................................... .............. 2-26 configuration and testing ...................................................................................................... .......................... 2-26 ieee 1149.1-compliant boundary scan testability................................................................................ 2-26 device configuration........................................................................................................... .................... 2-26 internal logic analyzer capability (isptracy).................................................................................. ..... 2-27 oscillator ..................................................................................................................... ............................ 2-27 density shifting ............................................................................................................... ................................. 2-28 dc and switching characteristics absolute maximum ratings ....................................................................................................... ........................ 3-1 recommended operating conditions ............................................................................................... ................. 3-1 hot socketing specifications................................................................................................... ........................... 3-2 dc electrical characteristics.................................................................................................. ............................ 3-3 supply current (sleep mode).................................................................................................... ......................... 3-3 supply current (standby)....................................................................................................... ............................ 3-4 initialization supply current .................................................................................................. ............................. 3-5 programming and erase flash supply current ..................................................................................... ............ 3-6 sysio recommended operating conditions......................................................................................... ............. 3-7 sysio single-ended dc electrical characteristics............................................................................... .............. 3-8 latticexp family handbook table of contents
table of contents lattice semiconductor latticexp family handbook 2 sysio differential electrical characteristics .................................................................................. ..................... 3-9 lvds........................................................................................................................... .............................. 3-9 differential hstl and sstl..................................................................................................... ........................ 3-10 lvds25e ........................................................................................................................ ........................ 3-10 blvds .......................................................................................................................... .......................... 3-10 lvpecl ......................................................................................................................... ......................... 3-12 rsds ........................................................................................................................... ........................... 3-12 typical building block function performance.................................................................................... .............. 3-14 pin-to-pin performance (lvcmos25 12 ma drive) ............................................................................... 3-1 4 register to register performance............................................................................................... ............ 3-14 derating logic timing .......................................................................................................... ............................ 3-15 latticexp external switching characteristics ................................................................................... ............... 3-16 latticexp internal timing parameters ........................................................................................... .................. 3-18 timing diagrams ................................................................................................................ .............................. 3-20 pfu timing diagrams............................................................................................................ ................. 3-20 ebr memory timing diagrams..................................................................................................... ................... 3-21 latticexp family timing adders ................................................................................................. ..................... 3-23 sysclock pll timing ............................................................................................................ ........................ 3-25 latticexp sysconfig port timing specifications................................................................................. .......... 3-26 flash download time ............................................................................................................ .......................... 3-27 jtag port timing specifications ................................................................................................ ..................... 3-27 switching test conditions...................................................................................................... .......................... 3-28 pinout information signal descriptions ............................................................................................................ ................................ 4-1 pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin .................................................... 4-3 pin information summary........................................................................................................ ........................... 4-4 power supply and nc connections................................................................................................ ................... 4-6 lfxp3 logic signal connections: 100 tqfp ....................................................................................... ............. 4-7 lfxp3 & lfxp6 logic signal connections: 144 tqfp............................................................................... .... 4-10 lfxp3 & lfxp6 logic signal connections: 208 pqfp ............................................................................... ... 4-14 lfxp6 & lfxp10 logic signal connections: 256 fpbga............................................................................. ... 4-19 lfxp15 & lfxp20 logic signal connections: 256 fpbga............................................................................ .. 4-26 lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga............................................................... 4-34 lfxp15 & lfxp20 logic signal connections: 484 fpbga............................................................................ .. 4-43 ordering information part number description........................................................................................................ ............................ 5-1 ordering information ........................................................................................................... ............................... 5-1 conventional packaging ......................................................................................................... .................. 5-2 lead-free packaging ............................................................................................................ ..................... 5-8 supplemental information for further information ........................................................................................................ .............................. 6-1 revision history revision history ............................................................................................................... .................................. 7-1 section ii. latticexp family technical notes latticeecp/ec and latticexp sysio usage guide introduction ................................................................................................................... ..................................... 8-1 sysio buffer overview .......................................................................................................... ............................. 8-1 supported sysio standards ...................................................................................................... ......................... 8-1 sysio banking scheme........................................................................................................... ........................... 8-2 v ccio (1.2v/1.5v/1.8v/2.5v/3.3v) .................................................................................................... ........ 8-3 v ccaux (3.3v) ........................................................................................................................ ................... 8-3 v ccj (1.2v/1.5v/1.8v/2.5v/3.3v).................................................................................................... .......... 8-3 input reference voltage (v ref1, v ref2 )................................................................................................... 8-3 v ref1 for ddr memory interface ...................................................................................................... ....... 8-3
table of contents lattice semiconductor latticexp family handbook 3 mixed voltage support in a bank................................................................................................ .............. 8-4 sysio standards supported in each bank......................................................................................... ................ 8-5 lvcmos buffer configurations ................................................................................................... ...................... 8-5 programmable pull-up/pull-down/buskeeper....................................................................................... .... 8-5 programmable drive ............................................................................................................. .................... 8-5 programmable slew rate ......................................................................................................... ................ 8-7 open drain control ............................................................................................................. ...................... 8-7 differential sstl and hstl support ............................................................................................. .................... 8-7 pci support with programmable pciclamp ......................................................................................... ........... 8-7 5v interface with pci clamp diode.............................................................................................. ...................... 8-8 programmable input delay ....................................................................................................... ......................... 8-9 software sysio attributes...................................................................................................... ............................. 8-9 io_type ........................................................................................................................ ........................... 8-9 opendrain...................................................................................................................... ..................... 8-10 drive .......................................................................................................................... ........................... 8-10 pullmode ....................................................................................................................... ..................... 8-11 pciclamp....................................................................................................................... ....................... 8-11 slewrate ....................................................................................................................... ..................... 8-11 fixeddelay..................................................................................................................... ..................... 8-11 din/dout....................................................................................................................... ........................ 8-11 loc............................................................................................................................ ............................. 8-12 design considerations and usage................................................................................................ ................... 8-12 banking rules .................................................................................................................. ....................... 8-12 differential i/o rules ......................................................................................................... ...................... 8-12 assigning v ref / v ref groups for referenced inputs............................................................................. 8-12 differential i/o implementation................................................................................................ ......................... 8-13 lvds........................................................................................................................... ............................ 8-13 blvds .......................................................................................................................... .......................... 8-13 rsds ........................................................................................................................... ........................... 8-13 lvpecl ......................................................................................................................... ......................... 8-13 differential sstl and hstl..................................................................................................... ............... 8-13 technical support assistance................................................................................................... ....................... 8-13 appendix a. hdl attributes for synplify and precision rtl synthesis ........................................................ 8-14 vhdl synplify/precision rtl synthesis.......................................................................................... ................ 8-14 syntax ......................................................................................................................... ............................ 8-14 examples ....................................................................................................................... ......................... 8-14 verilog for synplify ........................................................................................................... ................................ 8-17 syntax ......................................................................................................................... ............................ 8-17 examples ....................................................................................................................... ......................... 8-17 verilog for precision rtl synthesis............................................................................................ ..................... 8-19 syntax ......................................................................................................................... ............................ 8-19 example ........................................................................................................................ .......................... 8-19 appendix b. sysio attributes using preference editor user interface............................................................ . 8-21 appendix c. sysio attributes using preference file (ascii file) ................................................................ .... 8-22 iobuf .......................................................................................................................... ........................... 8-22 locate......................................................................................................................... ......................... 8-22 use din cell................................................................................................................... ..................... 8-23 use dout cell.................................................................................................................. .................. 8-23 pgroup vref .................................................................................................................... .................. 8-23 memory usage guide for latticeecp/ec and latticexp devices introduction ................................................................................................................... ..................................... 9-1 memories in latticeecp/ec and latticexp devices ................................................................................ ......... 9-1 utilizing ipexpress............................................................................................................ .................................. 9-3 ipexpress flow................................................................................................................. ......................... 9-3
table of contents lattice semiconductor latticexp family handbook 4 memory modules................................................................................................................. ............................... 9-7 single port ram (ram_dq) ?ebr based ........................................................................................... ... 9-7 true dual port ram (ram_dp_true) ?ebr based ........................................................................... 9-13 pseudo dual port ram (ram_dp) ?ebr-based.................................................................................. 9-22 read only memory (rom) ?ebr based............................................................................................. .. 9-25 first in first out (fifo, fifo_dc) ?ebr based................................................................................. .. 9-28 distributed single port ram (distributed_spram) ?pfu based.......................................................... 9-32 distributed dual port ram (distributed_dpram) ?pfu based ............................................................ 9-35 distributed rom (distributed_rom) ?pfu based ................................................................................ 9- 37 initializing memory ............................................................................................................ ............................... 9-39 initialization file format ..................................................................................................... ..................... 9-39 technical support assistance................................................................................................... ....................... 9-41 appendix a. attribute definitions.............................................................................................. ........................ 9-42 data_width..................................................................................................................... .................... 9-42 regmode........................................................................................................................ ...................... 9-42 resetmode ...................................................................................................................... ................... 9-42 csdecode....................................................................................................................... ..................... 9-42 writemode...................................................................................................................... .................... 9-42 gsr ............................................................................................................................ ............................ 9-42 latticeecp/ec and latticexp ddr usage guide introduction ................................................................................................................... ................................... 10-1 ddr sdram interfaces overview.................................................................................................. ................. 10-1 implementing ddr memory interfaces with the latticeecp/ec devices........................................................ 10-2 dqs grouping................................................................................................................... ...................... 10-2 ddr software primitives........................................................................................................ ................. 10-5 memory read implementation ..................................................................................................... ........... 10-9 data read critical path........................................................................................................ ................. 10-12 dqs postamble .................................................................................................................. .................. 10-13 memory write implementation .................................................................................................... .......... 10-14 design rules/guidelines........................................................................................................ ............... 10-16 qdr ii interface ............................................................................................................... ..................... 10-17 fcram (fast cycle random access memory) interface..................................................................... 10-17 generic high speed ddr implementation .......................................................................................... .......... 10-17 board design guidelines ........................................................................................................ ....................... 10-17 technical support assistance................................................................................................... ..................... 10-18 appendix a. using ipexpress to generate ddr modules.......................................................................... 1 0-19 ddr generic.................................................................................................................... ..................... 10-19 ddr memory interface ........................................................................................................... .............. 10-20 appendix b. verilog example for ddr input and output modules ................................................................ 10- 21 appendix c. vhdl example for ddr input and output modules.................................................................. 10-2 3 appendix d. generic (non-memory) high-speed ddr interface .................................................................. 10-2 8 vhdl implementation ............................................................................................................ ............... 10-28 verilog example ................................................................................................................ .................... 10-30 preference file................................................................................................................ ...................... 10-31 appendix e. list of compatible ddr sdram ....................................................................................... ........ 10-32 appendix f. ddr400 interface using the latticeec evaluation board.......................................................... 10-3 5 references..................................................................................................................... ................................ 10-36 latticeecp/ec and latticexp sysclock pll design and usage guide introduction ................................................................................................................... ................................... 11-1 features ....................................................................................................................... .................................... 11-1 functional description......................................................................................................... ............................. 11-1 pll divider and delay blocks................................................................................................... .............. 11-1 pll inputs and outputs ......................................................................................................... ................. 11-2 pll attributes................................................................................................................. ......................... 11-3
table of contents lattice semiconductor latticexp family handbook 5 latticeecp/ec and latticexp pll primitive definitions.......................................................................... ........ 11-4 pll attributes definitions..................................................................................................... ................... 11-4 dynamic delay adjustment ....................................................................................................... .............. 11-6 pll usage in ipexpress......................................................................................................... .......................... 11-7 including sysclock plls in a design............................................................................................ ....... 11-7 ipexpress usage................................................................................................................ ..................... 11-7 ehxpllb example projects ....................................................................................................... ............ 11-9 equations for generating input and output frequency ranges .................................................................... 1 1-10 f vco constraint .................................................................................................................... ................. 11-10 f pfd constraint .................................................................................................................... .................. 11-10 clock distribution in latticeecp/ec and latticexp .............................................................................. ......... 11-11 primary clock sources and distribution......................................................................................... ....... 11-11 restrictions to primary clock net usage ........................................................................................ ...... 11-12 limitations on secondary clock availability.................................................................................... ...... 11-12 maximum number of global clocks and quadrant clocks as primary clocks..................................... 11-13 dynamic clock selection (dcs) .................................................................................................. .................. 11-13 dcs waveforms .................................................................................................................. ................. 11-14 use of dcs with pll ............................................................................................................ ................ 11-16 other design considerations .................................................................................................... ..................... 11-16 jitter considerations .......................................................................................................... ................... 11-16 simulation limitations ......................................................................................................... .................. 11-17 pcb layout recommendations for vccpll and gndpll if separate pins are available ................. 11-17 dcs usage with verilog......................................................................................................... ............... 11-17 dcs usage with vhdl ............................................................................................................ ...................... 11-17 technical support assistance................................................................................................... ..................... 11-18 estimating power using the power calculator for latticeecp/ec and latticexp devices introduction ................................................................................................................... ................................... 12-1 power supply sequencing and hot socketing...................................................................................... ........... 12-1 power calculator hardware assumptions.......................................................................................... .............. 12-1 power calculator............................................................................................................... ............................... 12-1 power calculator equations..................................................................................................... ............... 12-2 starting the power calculator .................................................................................................. ............... 12-3 starting a power calculator project ............................................................................................ ............ 12-5 power calculator main window ................................................................................................... ........... 12-6 power calculator wizard........................................................................................................ ................. 12-8 power calculator ?creating a new project without the ncd file ....................................................... 12-13 power calculator ?creating a new project with the ncd file ............................................................ 12-14 power calculator ?open existing project ....................................................................................... ..... 12-16 power calculator ?total power................................................................................................. ........... 12-17 activity factor................................................................................................................ ................................. 12-17 ambient and junction temperature and airflow ................................................................................... ......... 12-18 managing power consumption ..................................................................................................... ................. 12-18 power calculator assumptions ................................................................................................... ................... 12-19 technical support assistance................................................................................................... ..................... 12-19 appendix a. power calculator project example ................................................................................... ......... 12-20 latticexp sysconfig usage guide introduction ................................................................................................................... ................................... 13-1 programming overview........................................................................................................... ......................... 13-1 configuration pins............................................................................................................. ............................... 13-2 dedicated pins ................................................................................................................. ....................... 13-3 dual-purpose sysconfig pins.................................................................................................... .......... 13-7 ispjtag pins ................................................................................................................... ....................... 13-8 configuration and jtag voltage levels .......................................................................................... ....... 13-9 configuration modes and options................................................................................................ .................... 13-9
table of contents lattice semiconductor latticexp family handbook 6 configuration options .......................................................................................................... ................. 13-10 slave serial mode .............................................................................................................. ................... 13-11 master serial mode ............................................................................................................. .................. 13-11 slave parallel mode ............................................................................................................ .................. 13-12 self download mode ............................................................................................................. ................ 13-14 ispjtag mode ................................................................................................................... ................... 13-14 wake up options ................................................................................................................ ........................... 13-15 wake up sequence ............................................................................................................... ............... 13-15 software selectable options.................................................................................................... ...................... 13-16 persistent ..................................................................................................................... ......................... 13-17 configuration mode............................................................................................................. .................. 13-17 done open drain ................................................................................................................ ................ 13-17 done external.................................................................................................................. .................... 13-18 master clock selection ......................................................................................................... ................ 13-18 security ....................................................................................................................... .......................... 13-18 wake up sequence ............................................................................................................... ............... 13-18 wake up clock selection........................................................................................................ .............. 13-18 power save..................................................................................................................... ...................... 13-18 technical support assistance................................................................................................... ..................... 13-19 lattice isptracy usage guide introduction ................................................................................................................... ................................... 14-1 isptracy ip core features ...................................................................................................... ...................... 14-1 isptracy ip module generator ................................................................................................... ................... 14-1 isptracy core generator ........................................................................................................ ...................... 14-2 isptracy core linker........................................................................................................... .......................... 14-4 isptracy ispla program......................................................................................................... ....................... 14-6 conclusion ..................................................................................................................... .................................. 14-9 references..................................................................................................................... .................................. 14-9 technical support assistance................................................................................................... ....................... 14-9 hdl synthesis coding guidelines for lattice semiconductor fpgas introduction ................................................................................................................... ................................... 15-1 general coding styles for fpga ................................................................................................. .................... 15-1 hierarchical coding............................................................................................................ ..................... 15-1 design partitioning ............................................................................................................ ...................... 15-2 state encoding methodologies for state machines ................................................................................ 15-3 coding styles for fsm .......................................................................................................... .................. 15-5 using pipelines in the designs................................................................................................. ............... 15-6 comparing if statement and case statement ...................................................................................... . 15-7 avoiding non-intentional latches............................................................................................... ............. 15-8 hdl design with lattice semiconductor fpga devices ............................................................................. .... 15-8 lattice semiconductor fpga synthesis library ................................................................................... .. 15-8 implementing multiplexers ...................................................................................................... .............. 15-10 clock dividers ................................................................................................................. ...................... 15-10 register control signals ....................................................................................................... ................ 15-12 use pic features............................................................................................................... ................... 15-14 implementation of memories..................................................................................................... ............ 15-16 preventing logic replication and limited fanout................................................................................ . 15-16 use isplever project navigator results for device utilization and performance .............................. 15-17 technical support assistance................................................................................................... ..................... 15-17 lattice semiconductor design floorplanning introduction ................................................................................................................... ................................... 16-1 supported architectures........................................................................................................ ........................... 16-1 related documentation.......................................................................................................... .......................... 16-1 floorplanning definition ....................................................................................................... ............................ 16-1
table of contents lattice semiconductor latticexp family handbook 7 complex fpga design management ................................................................................................. ............. 16-1 floorplanning design flow...................................................................................................... ......................... 16-2 when to floorplan.............................................................................................................. .............................. 16-2 floorplan to improve design performance ........................................................................................ .............. 16-3 floorplan to preserve module performance ....................................................................................... ............. 16-3 floorplan for design reuse ..................................................................................................... ........................ 16-3 how to floorplan a design...................................................................................................... ......................... 16-4 design performance enhancement strategies ...................................................................................... . 16-4 design floorplanning methodologies............................................................................................. ......... 16-4 when to use pgroup vs. ugroup .................................................................................................. ... 16-4 floorplanner gui usage ......................................................................................................... ................ 16-6 special floorplanning considerations........................................................................................... ................... 16-7 embedded block ram placement ................................................................................................... ....... 16-7 i/o grouping................................................................................................................... ......................... 16-7 large module grouping .......................................................................................................... ................ 16-7 carry chains and bus grouping .................................................................................................. ........... 16-7 slics in groups................................................................................................................ ...................... 16-7 summary........................................................................................................................ .................................. 16-7 technical support assistance................................................................................................... ....................... 16-8 lattice semiconductor fpga successful place and route introduction ................................................................................................................... ................................... 17-1 isplever place and route software (par) ........................................................................................ ........... 17-1 placement ...................................................................................................................... ......................... 17-1 routing........................................................................................................................ ............................ 17-1 timing driven par process...................................................................................................... .............. 17-2 general strategy guidelines .................................................................................................... ........................ 17-2 typical design preferences ..................................................................................................... ............... 17-2 proper preferences ............................................................................................................. .................... 17-3 translating board requirements into fpga preferences ...................................................................... 17-4 analyzing timing reports ....................................................................................................... ......................... 17-6 example 1. multicycle between two different clocks ............................................................................ 1 7-6 example 2. clock_to_out with pll feedback................................................................................. 17-8 isplever controlled place and route............................................................................................ .............. 17-10 running multiple routing passes ................................................................................................ ......... 17-10 using multiple placement iterations (cost tables) .............................................................................. . 17-11 clock boosting ................................................................................................................. ..................... 17-12 guided map and par ............................................................................................................. ....................... 17-14 notes on guided mapping ........................................................................................................ ............ 17-15 notes on guided par............................................................................................................ ............... 17-15 conclusion ..................................................................................................................... ................................ 17-15 technical support assistance................................................................................................... ..................... 17-16 board timing guidelines for the ddr sdram controller ip core introduction ................................................................................................................... ................................... 18-1 read operation................................................................................................................. ............................... 18-2 set-up time calculation for the data input (max. case) ........................................................................ 1 8-3 hold time calculation for the data input (min. case)........................................................................... .. 18-3 write operation ................................................................................................................ ................................ 18-4 write set-up ................................................................................................................... ......................... 18-4 write hold ..................................................................................................................... .......................... 18-5 address and command signals.................................................................................................... ................... 18-5 set-up calculation............................................................................................................. ...................... 18-6 hold calculation ............................................................................................................... ....................... 18-7 board design guidelines ........................................................................................................ ......................... 18-7 technical support assistance................................................................................................... ....................... 18-8
table of contents lattice semiconductor latticexp family handbook 8 appendix a. example extractions of delays from timing reports .................................................................. 18-9 pcb layout recommendations for bga packages introduction ................................................................................................................... ................................... 19-1 advantages and disadvantages of bga packaging .................................................................................. ...... 19-1 pcb layout ..................................................................................................................... ................................. 19-2 plated through hole (via) placement............................................................................................ .................. 19-2 bga board layout recommendations ............................................................................................... ............. 19-3 bga package types.............................................................................................................. .......................... 19-3 fpbga (fine pitch bga)......................................................................................................... ................. 19-3 fpsbga (fine pitch sbga)....................................................................................................... .............. 19-3 ftbga (fine pitch thin bga):................................................................................................... ............... 19-3 fcbga (flip chip bga).......................................................................................................... .................. 19-3 cabga (chip array bga)......................................................................................................... ............... 19-3 csbga (chip scale bga)......................................................................................................... ............... 19-3 pbga (plastic bga)............................................................................................................. ................... 19-3 sbga (super bga)............................................................................................................... .................. 19-3 further information............................................................................................................ ............................... 19-3 technical support assistance................................................................................................... ....................... 19-3 revision history ............................................................................................................... ................................ 19-4 section iii. latticexp family handbook revision history revision history ............................................................................................................... ................................ 20-1
section i. latticexp family data sheet ds1001 version 04.9, february 2007
december 2005 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 1-1 ds1001 introduction_01.4 features non-volatile, in?itely recon?urable instant-on ?powers up in microseconds no external con?uration memory excellent design security, no bit stream to intercept recon?ure sram based logic in milliseconds sram and non-volatile memory programmable through system con?uration and jtag ports sleep mode allows up to 1000x static current reduction transfr recon?uration (tfr) in-?ld logic update while system operates extensive density and package options 3.1k to 19.7k lut4s 62 to 340 i/os density migration supported embedded and distributed memory 54 kbits to 396 kbits sysmem embedded block ram up to 79 kbits distributed ram flexible memory resources: ? distributed and block memory flexible i/o buffer programmable sysio buffer supports wide range of interfaces: ? lvcmos 3.3/2.5/1.8/1.5/1.2 ? lvttl sstl 18 class i ? sstl 3/2 class i, ii hstl15 class i, iii ? hstl 18 class i, ii, iii ? pci ? lvds, bus-lvds, lvpecl, rsds dedicated ddr memory support implements interface up to ddr333 (166mhz) sysclock plls up to 4 analog plls per device clock multiply, divide and phase shifting system level support ieee standard 1149.1 boundary scan, plus isptracy internal logic analyzer capability onboard oscillator for con?uration devices operate with 3.3v, 2.5v, 1.8v or 1.2v power supply table 1-1. latticexp family selection guide device lfxp3 lfxp6 lfxp10 lfxp15 lfxp20 pfu/pff rows 16 24 32 40 44 pfu/pff columns 24 30 38 48 56 pfu/pff (total) 384 720 1216 1932 2464 luts (k) 3.1 5.8 9.7 15.4 19.7 distributed ram (kbits) 12 23 39 61 79 ebr sram (kbits) 54 72 216 324 396 ebr sram blocks 6 8 24 36 44 v cc voltage 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v plls 22444 max. i/o 136 188 244 300 340 packages and i/o combinations: 100-pin tqfp (14 x 14 mm) 62 144-pin tqfp (20 x 20 mm) 100 100 208-pin pqfp (28 x 28 mm) 136 142 256-ball fpbga (17 x 17 mm) 188 188 188 188 388-ball fpbga (23 x 23 mm) 244 268 268 484-ball fpbga (23 x 23 mm) 300 340 latticexp family data sheet introduction
introduction lattice semiconductor latticexp family data sheet 1-2 introduction the latticexp family of fpga devices combine logic gates, embedded memory and high performance i/os in a single architecture that is both non-volatile and in?itely recon?urable to support cost-effective system designs. the re-programmable non-volatile technology used in the latticexp family is the next generation ispxp technol- ogy. with this technology, expensive external con?uration memories are not required and designs are secured from unauthorized read-back. in addition, instant-on capability allows for easy interfacing in many applications. the isplever design tool from lattice allows large complex designs to be ef?iently implemented using the lat- ticexp family of fpga devices. synthesis library support for latticexp is available for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constraints from its ?or planning tools to place and route the design in the latticexp device. the isplever tool extracts the timing from the routing and back- annotates it into the design for timing veri?ation. lattice provides many pre-designed ip (intellectual property) isplevercore modules for the latticexp family. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
february 2007 data sheet ds1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 2-1 ds1001 architecture_01.9 architecture overview the latticexp architecture contains an array of logic blocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) as shown in figure 2- 1. on the left and right sides of the pfu array, there are non-volatile memory blocks. in con?uration mode this non- volatile memory is programmed via the ieee 1149.1 tap port or the sysconfig peripheral port. on power up, the con?uration data is transferred from the non-volatile memory blocks to the con?uration sram. with this technology, expensive external con?uration memories are not required and designs are secured from unautho- rized read-back. this transfer of data from non-volatile memory to con?uration sram via wide busses happens in microseconds, providing an ?nstant-on capability that allows easy interfacing in many applications. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram/rom (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom and register func- tions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for ?xibility, allowing complex designs to be implemented quickly and ef?iently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. the pfu blocks are used on the out- side rows. the rest of the core consists of rows of pff blocks interspersed with rows of pfu blocks. for every three rows of pff blocks there is a row of pfu blocks. each pic block encompasses two pios (pio pairs) with their respective sysio interfaces. pio pairs on the left and right edges of the device can be con?ured as lvds transmit/receive pairs. sysmem ebrs are large dedicated fast memory blocks. they can be con?ured as ram or rom. the pfu, pff, pic and ebr blocks are arranged in a two-dimensional grid with rows and columns as shown in figure 2-1. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. at the end of the rows containing the sysmem blocks are the sysclock phase locked loop (pll) blocks. these plls have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. the latticexp architecture provides up to four plls per device. every device in the family has a jtag port with internal logic analyzer (isptracy) capability. the sysconfig port which allows for serial or parallel device con?uration. the latticexp devices are available for operation from 3.3v, 2.5v, 1.8v and 1.2v power supplies, providing easy integration into the overall system. latticexp family data sheet architecture
2-2 architecture lattice semiconductor latticexp family data sheet figure 2-1. latticexp top level block diagram pfu and pff blocks the core of the latticexp devices consists of pfu and pff blocks. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remainder of the data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-2. all the interconnec- tions to and from pfu blocks are from routing. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-2. pfu diagram programmable i/o cell (pic) includes sysio interface non-volatile memory sysconfig programming port (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (pfu without ram) jtag port sysmem embedded block ram (ebr) slice 0 lut4 & carry lut4 & carry ff/ latch d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d
2-3 architecture lattice semiconductor latticexp family data sheet slice each slice contains two lut4 lookup tables feeding two registers (programmed to be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-3 shows an overview of the internal logic of the slice. the registers in the slice can be con?ured for positive/negative and edge/level clocks. there are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or pfu). there are 7 outputs: 6 to routing and one to carry-chain (to adjacent pfu). table 2-1 lists the signals associated with each slice. figure 2-3. slice diagram lut4 & carry lut4 & carry slice a0 b0 c0 d0 ff/ latch ofx0 f0 q0 a1 b1 c1 d1 ci ci co co f sum ce clk lsr ff/ latch ofx1 f1 q1 f sum d d m1 to / from different slice / pfu fast carry out (fco) to / from different slice / pfu fast carry in (fci) lut expansion mux m0 ofx0 from routing to routing control signals selected and inverted per slice in routing note: some interslice signals are not shown.
2-4 architecture lattice semiconductor latticexp family data sheet table 2-1. slice signal descriptions modes of operation each slice is capable of four modes of operation: logic, ripple, ram and rom. the slice in the pff is capable of all modes except ram. table 2-2 lists the modes and the capability of the slice blocks. table 2-2. slice modes logic mode: in this mode, the luts in each slice are con?ured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any logic function with four inputs can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger lookup tables such as lut6, lut7 and lut8 can be constructed by concatenating other slices. ripple mode: ripple mode allows the ef?ient implementation of small arithmetic functions. in ripple mode, the fol- lowing functions can be implemented by each slice: addition 2-bit subtraction 2-bit add/subtract 2-bit using dynamic control up counter 2-bit down counter 2-bit ripple mode multiplier building block comparator functions of a and b inputs - a greater-than-or-equal-to b - a not-equal-to b - a less-than-or-equal-to b two additional signals: carry generate and carry propagate are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. ram mode: in this mode, distributed ram can be constructed using each lut block as a 16x1-bit memory. through the combination of luts and slices, a variety of different memories can be constructed. function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco for the right most pfu the fast carry chain output 1 1. see figure 2-2 for connection details. 2. requires two pfus. logic ripple ram rom pfu slice lut 4x2 or lut 5x1 2-bit arithmetic unit sp 16x2 rom 16x1 x 2 pff slice lut 4x2 or lut 5x1 2-bit arithmetic unit n/a rom 16x1 x 2
2-5 architecture lattice semiconductor latticexp family data sheet the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. figure 2-4 shows the dis- tributed memory primitive block diagrams. dual port memories involve the pairing of two slices, one slice functions as the read-write port. the other companion slice supports the read-only port. for more information on ram mode in latticexp devices, please see details of additional technical documentation at the end of this data sheet. table 2-3. number of slices required for implementing distributed ram figure 2-4. distributed memory primitives rom mode: the rom mode uses the same principal as the ram modes, but without the write port. pre-loading is accomplished through the programming interface during con?uration. pfu modes of operation slices can be combined within a pfu to form larger functions. table 2-4 tabulates these modes and documents the functionality possible at the pfu level. spr16x2 dpr16x2 number of slices 1 2 note: spr = single port ram, dpr = dual port ram do1 do0 di0 di1 ad0 ad1 ad2 ad3 wre ck do0 ad0 ad1 ad2 ad3 dpr16x2 spr16x2 rom16x1 rdo1 rdo0 di0 di1 wck wre wdo1 wdo0 wad0 wad1 wad2 wad3 rad0 rad1 rad2 rad3
2-6 architecture lattice semiconductor latticexp family data sheet table 2-4. pfu modes of operation routing there are many resources provided in the latticexp devices to route signals individually or as buses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and ef?ient connections in horizontal, vertical and diagonal directions. the x2 and x6 resources are buffered allowing both short and long connections routing between pfus. the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. clock distribution network the clock inputs are selected from external i/o, the sysclock plls or routing. these clock inputs are fed through the chip via a clock distribution system. primary clock sources latticexp devices derive clocks from three primary sources: pll outputs, dedicated clock inputs and routing. lat- ticexp devices have two to four sysclock plls, located on the left and right sides of the device. there are four dedicated clock inputs, one on each side of the device. figure 2-5 shows the 20 primary clock sources. logic ripple ram 1 rom lut 4x8 or mux 2x1 x 8 2-bit add x 4 spr16x2 x 4 dpr16x2 x 2 rom16x1 x 8 lut 5x4 or mux 4x1 x 4 2-bit sub x 4 spr16x4 x 2 dpr16x4 x 1 rom16x2 x 4 lut 6x 2 or mux 8x1 x 2 2-bit counter x 4 spr16x8 x 1 rom16x4 x 2 lut 7x1 or mux 16x1 x 1 2-bit comp x 4 rom16x8 x 1 1. these modes are not available in pff blocks
2-7 architecture lattice semiconductor latticexp family data sheet figure 2-5. primary clock sources secondary clock sources latticexp devices have four secondary clock resources per quadrant. the secondary clock branches are tapped at every pfu. these secondary clock networks can also be used for controls and high fanout data. these secondary clocks are derived from four clock input pads and 16 routing signals as shown in figure 2-6. from routing clock input from routing pll input clock input pll input pll input clock input pll input from routing clock input from routing pll pll pll pll 20 primary clock sources to quadrant clock selection note: smaller devices have two plls.
2-8 architecture lattice semiconductor latticexp family data sheet figure 2-6. secondary clock sources clock routing the clock routing structure in latticexp devices consists of four primary clock lines and a secondary clock net- work per quadrant. the primary clocks are generated from muxs located in each quadrant. figure 2-7 shows this clock routing. the four secondary clocks are generated from muxs located in each quadrant as shown in figure 2- 8. each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in figure 2- 9. figure 2-7. per quadrant primary clock selection 20 secondary clock sources to quadrant clock selection from routing from routing clock input clock input from routing from routing from routing from routing from routing from routing from routing from routing from routing clock input clock input from routing from routing from routing from routing from routing 4 primary clocks (clk0, clk1, clk2, clk3) per quadrant 20 primary clock sources: 12 plls + 4 pios + 4 routing 1 dcs 2 dcs 2 1. smaller devices have fewer pll related lines. 2. dynamic clock select.
2-9 architecture lattice semiconductor latticexp family data sheet figure 2-8. per quadrant secondary clock selection figure 2-9. slice clock selection sysclock phase locked loops (plls) the pll clock input, from pin or routing, feeds into an input clock divider. there are three sources of feedback sig- nals to the feedback divider: from clkop (pll internal), from clock net (clkop or clkos) or from a user clock (pin or logic). there is a pll_lock signal to indicate that vco has locked on to the input clock signal. figure 2-10 shows the sysclock pll diagram. the setup and hold times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. this delay can be either pro- grammed during con?uration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after adjustment and not relock until the t lock parameter has been satis?d. additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the clkos output. the sysclock plls provide the ability to synthesize clock frequencies. each pll has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. the input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. the post scalar divider allows the vco to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. the secondary divider is used to derive lower frequency outputs. 4 secondary clocks per quadrant 20 secondary clock feedlines : 4 clock input pads + 16 routing signals primary clock secondary clock routing clock to each slice gnd
2-10 architecture lattice semiconductor latticexp family data sheet figure 2-10. pll diagram figure 2-11 shows the available macros for the pll. table 2-11 provides signal description of the pll block. figure 2-11. pll primitive table 2-5. pll signal descriptions signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) rst i ? to reset input clock divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ? indicates pll lock to clki ddamode i dynamic delay enable. ? pin control (dynamic), ?? fuse control (static) ddaizr i dynamic delay zero. ?? delay = 0, ?? delay = on ddailag i dynamic delay lag/lead. ?? lag, ?? lead ddaidel[2:0] i dynamic delay input ddaozr o dynamic delay zero output ddaolag o dynamic delay lag/lead output ddaodel[2:0] o dynamic delay output vco clkos clkok lock rst clkfb from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) dynamic delay adjustment input clock divider (clki) feedback divider (clkfb) post scalar divider (clkop) phase/duty select secondary clock divider (clkok) delay adjust voltage controlled oscillator clki (from routing or external pin) clkop epllb clkop clki clkfb lock ehxpllb clkos clki clkfb clkok lock rst clkop ddaizr ddailag dda mode ddaidel[2:0] ddaozr ddaolag ddaodel[2:0]
2-11 architecture lattice semiconductor latticexp family data sheet for more information on the pll, please see details of additional technical documentation at the end of this data sheet. dynamic clock select (dcs) the dcs is a global clock buffer with smart multiplexer functions. it takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. this is achieved irrespective of where the select signal is toggled. there are eight dcs blocks per device, located in pairs at the center of each side. figure 2-12 illustrates the dcs block macro. figure 2-12. dcs block primitive figure 2-13 shows timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information on the dcs, please see details of additional technical documentation at the end of this data sheet. figure 2-13. dcs waveforms sysmem memory the latticexp family of devices contain a number of sysmem embedded block ram (ebr). the ebr consists of a 9-kbit ram, with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. dcs clk0 dcsout clk1 sel clk0 sel dcsout clk1
2-12 architecture lattice semiconductor latticexp family data sheet table 2-6. sysmem block con?urations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1 and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con?uration. by preloading the ram block during the chip con?uration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? design inputs. single, dual and pseudo-dual port modes figure 2-14 shows the four basic memory con?urations and their input/output names. in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. memory mode con?urations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 true dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36
2-13 architecture lattice semiconductor latticexp family data sheet figure 2-14. sysmem memory primitives the ebr memory supports three forms of write behavior for single port or dual port operation: 1. normal ?data on the output appears only during read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through - a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. 3. read-before-write ?when new data is being written, the old content of the address appears at the output. this mode is supported for x9, x18 and x36 data widths. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respec- tively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-15. ebr ad[12:0] di[35:0] clk ce rst we cs[2:0] do[35:0] single port ram ebr true dual port ram pseudo-dual port ram rom ad[12:0] clk ce do[35:0] rst cs[2:0] ebr ebr ada[12:0] dia[17:0] clka cea rsta wea csa[2:0] doa[17:0] adb[12:0] dib[17:0] clkb ceb rstb web csb[2:0] dob[17:0] adw[12:0] di[35:0] clkw cew adr[12:0] do[35:0] cer clkr we rst cs[2:0]
2-14 architecture lattice semiconductor latticexp family data sheet figure 2-15. memory core reset for further information on sysmem ebr block, see the details of additional technical documentation at the end of this data sheet. ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-16. the gsr input to the ebr is always asynchronous. figure 2-16. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during con?uration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restrictions if the ebr synchronous reset is used and the ebr gsr input is disabled. programmable i/o cells (pics) each pic contains two pios connected to their respective sysio buffers which are then connected to the pads as shown in figure 2-17. the pio block supplies the output data (do) and the tri-state control signal (to) to sysio buffer, and receives input from the buffer. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr reset clock clock ena b le
2-15 architecture lattice semiconductor latticexp family data sheet figure 2-17. pic diagram in the latticexp family, seven pios or four (3.5) pics are grouped together to provide two lvds differential pairs, one pic pair and one single i/o, as shown in figure 2-18. two adjacent pios can be joined to provide a differential i/o pair (labeled as ? and ??. the pad labels ? and ? distinguish the two pios. only the pio pairs on the left and right edges of the device can be con?ured as lvds transmit/receive pairs. one of every 14 pios (a group of 8 pics) contains a delay element to facilitate the generation of dqs signals as shown in figure 2-19. the dqs signal feeds the dqs bus which spans the set of 13 pios (8 pics). the dqs sig- nal from the bus is used to strobe the ddr data from the memory into input register blocks. this interface is designed for memories that support one dqs strobe per eight bits of data. the exact dqs pins are shown in a dual function in the logic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table in this data sheet. pio b pa da "t" padb ? opos0 oneg0 opos1 oneg1 td inck indd inff ipos0 ipos1 clk ce lsr gsrn clko clki ceo cei pio a sysio buffer control muxes lsr gsr dqs ddrclkpol iold0 iolt0 d0 ddrclk di ipos1 ipos0 inck indd inff d0 d1 td d1 do tristate register block (2 flip flops) output register block (2 flip flops) ddrclk input register block (5 flip flops)
2-16 architecture lattice semiconductor latticexp family data sheet figure 2-18. group of seven pios figure 2-19. dqs routing pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for both single data rate (sdr) and double data rate (ddr) operation along with the necessary clock and selection logic. programmable delay lines used to shift incoming clock and data sig- nals are also included in these blocks. input register block the input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. figure 2-20 shows the diagram of the input register block. input signals are fed from the sysio buffer to the input register block (as signal di). if desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and pio a pio b pio a pio b pio a pio a pio b pada ? padb ? lvds pair pada ? padb ? pada ? padb ? lvds pair pada ? four pics one pio pair pio a pio b pada ? padb ? pio b pio a assigned dqs pin dqs sysio buffer lvds pair lvds pair pio a pio b pada ? padb ? pio a pio b pada ? padb ? lvds pair pio a pada ? pio b pada ? padb ? padb ? pio a pio b pada ? padb ? pio a pio b pada ? padb ? lvds pair delay
2-17 architecture lattice semiconductor latticexp family data sheet in selected blocks the input to the dqs delay block. if one of the bypass options is not chosen, the signal ?st passes through an optional delay block. this delay, if selected, ensures no positive input-register hold-time require- ment when using a global clock. the input block allows two modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in the ddr mode two registers are used to sample the data on the positive and negative edges of the dqs signal creating two data streams, d0 and d2. these two data streams are synchronized with the system clock before entering the core. further discussion on this topic is in the ddr memory section of this data sheet. figure 2-21 shows the input register waveforms for ddr operation and figure 2-22 shows the design tool primi- tives. the sdr/sync registers have reset and clock enable available. the signal ddrclkpol controls the polarity of the clock used in the synchronization registers. it ensures ade- quate timing when data is transferred from the dqs to the system clock domain. for further discussion of this topic, see the ddr memory section of this data sheet. figure 2-20. input register diagram d q d q d q d-type fixed delay to routing di (from sysio buffer) dqs delayed (from dqs bus) clk0 (from routing) ddrclkpol (from ddr polarity control bus) inck indd delay block ddr registers d-type d-type d q d q d-type /latch /latch d-type ipos0 ipos1 sdr & sync registers d0 d2 d1
2-18 architecture lattice semiconductor latticexp family data sheet figure 2-21. input register ddr waveforms figure 2-22. inddrxb primitive output register block the output register block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-23 shows the diagram of the output register block. in sdr mode, oneg0 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured as a d- type or as a latch. in ddr mode, oneg0 is fed into one register on the positive edge of the clock and opos0 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). figure 2-24 shows the design tool ddr primitives. the sdr output register has reset and clock enable available. the additional register for ddr operation does not have reset or clock enable available. abcde f bd di (in ddr mode) d0 d2 dqs a c dqs delayed iddrxb lsr qa d eclk qb ddrclkpol sclk ce
2-19 architecture lattice semiconductor latticexp family data sheet figure 2-23. output register block figure 2-24. oddrxb primitive tristate register block the tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-25 shows the diagram of the tristate register block. in sdr mode, oneg1 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured a d- type or latch. in ddr mode, oneg1 is fed into one register on the positive edge of the clock and opos1 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). d q d q d-type oneg0 from routing clk1 *latch is transparent when input is low. programmed control do opos0 outddn /latch latch le* 0 1 0 1 to sysio buffer oddrxb lsr q db clk da
2-20 architecture lattice semiconductor latticexp family data sheet figure 2-25. tristate register block control logic block the control logic block allows the selection and modi?ation of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing and a dqs signal provided from the programmable dqs pin. the clock can optionally be inverted. the clock enable and local reset signals are selected from the routing and optionally inverted. the global tristate signal is passed through this block. ddr memory support implementing high performance ddr memory interfaces requires dedicated ddr register structures in the input (for read operations) and in the output (for write operations). as indicated in the pio logic section, the latticexp devices provide this capability. in addition to these registers, the latticexp devices contain two elements to simplify the design of input structures for read operations: the dqs delay block and polarity control logic. dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment, however in ddr memories the clock (referred to as dqs) is not free running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. the dqs signal (selected pios only) feeds from the pad through a dqs delay element to a dedicated dqs rout- ing resource. the dqs signal also feeds the polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figures 2-26 and 2-27 show how the polarity control logic are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dlls on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-27. the dll loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. d le* q d q d-type oneg1 clk1 programmed control to opos1 outddn /latch latch 0 1 0 1 from routing to sysio buffer td *latch is transparent when input is low.
2-21 architecture lattice semiconductor latticexp family data sheet figure 2-26. dqs local bus figure 2-27. dll calibration bus and dqs/dqs transition distribution di clki cei pio gsr dqs input register block ( 5 flip flops) to sync. reg. dqs to ddr reg. dqs strobe pa d ddr datain pa d sysio buffer di sysio buffer pio dqsdel polarity control logic dqs calibration bus from dll delay control bus polarity control bus dqs bus dll dll polarity control signal bus dqs signal bus delay control bus
2-22 architecture lattice semiconductor latticexp family data sheet polarity control logic in a typical ddr memory interface design, the phase relation between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticexp family contains dedicated circuits to transfer data between these domains. to prevent setup and hold violations at the domain transfer between dqs (delayed) and the system clock a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register block. this requires evaluation at the start of the each read cycle for the correct clock polarity. prior to the read operation in ddr memories dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects this transition. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer each i/o is associated with a ?xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in eight groups referred to as banks. the sysio buffers allow users to implement the wide variety of standards that are found in todays systems including lvcmos, sstl, hstl, lvds and lvpecl. sysio buffer banks latticexp devices have eight sysio buffer banks; each is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ), and two voltage references v ref1 and v ref2 resources allowing each bank to be completely independent from each other. figure 2-28 shows the eight banks and their associated sup- plies. in the latticexp devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos, pci and pci-x) are powered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as a ?ed threshold input independent of v ccio. in addition to the bank v ccio supplies, the latticexp devices have a v cc core logic power sup- ply, and a v ccaux supply that power all differential and referenced buffers. each bank can support up to two separate vref voltages, vref1 and vref2 that set the threshold for the refer- enced input buffers. in the latticexp devices, a dedicated pin in a bank can be con?ured to be a reference voltage supply pin. each i/o is individually con?urable based on the banks supply and reference voltages.
2-23 architecture lattice semiconductor latticexp family data sheet figure 2-28. latticexp banks latticexp devices contain two types of sysio buffer pairs. 1. top and bottom sysio buffer pair (single-ended outputs only) the sysio buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be con?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. only the i/os on the top and bottom banks have pci clamps. note that the pci clamp is enabled after v cc, v ccaux and v ccio are at valid operating levels and the device has been con?ured. 2. left and right sysio buffer pair (differential and single-ended outputs) the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. the refer- enced input buffer can also be con?ured as a differential input. in these banks the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. select i/os in the left and right banks have lvds differential output drivers. refer to the logic signal connec- tions tables for more information. v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd note: n and m are the maximum number of i/os per bank. bank 6 v ccio6 v ref2(6) v ref1(5) gnd bank 5 v ccio5 v ref2(5) v ref1(4) gnd bank 4 v ccio4 v ref2(4) v ref1( 0) gnd bank 0 v ccio0 v ref2( 0) v ref1(1) gnd bank 1 v ccio1 v ref2(1) 1 m 1 m 1 m 1 m 1n 1n 1n 1n
2-24 architecture lattice semiconductor latticexp family data sheet typical i/o behavior during power-up the internal power-on-reset (por) signal is deactivated when v cc and v ccaux have reached satisfactory levels. after the por signal is deactivated, the fpga core logic becomes active. it is the users responsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. the default con?uration of the i/o pins in a blank device is tri-state with a weak pull-up to vccio. the i/o pins will maintain the blank con?uration until vcc, vccaux and vccio have reached satisfactory levels at which time the i/os will take on the user-con?ured settings. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buff- ers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered up before or together with the v cc and v ccaux supplies. supported standards the latticexp sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually con?urable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other sin- gle-ended standards supported include sstl and hstl. differential standards supported include lvds, blvds, lvpecl, differential sstl and differential hstl. tables 2-7 and 2-8 show the i/o standards (together with their supply and reference voltages) supported by the latticexp devices. for further information on utilizing the sysio buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. table 2-7. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lvttl lvcmos33 2 lvcmos25 2 lvcmos18 1.8 lvcmos15 1.5 lvcmos12 2 pci 3.3 hstl18 class i, ii 0.9 hstl18 class iii 1.08 hstl15 class i 0.75 hstl15 class iii 0.9 sstl3 class i, ii 1.5 sstl2 class i, ii 1.25 sstl18 class i 0.9 differential interfaces differential sstl18 class i differential sstl2 class i, ii differential sstl3 class i, ii differential hstl15 class i, iii differential hstl18 class i, ii, iii lvds, lvpecl blvds 1. when not speci?d v ccio can be set anywhere in the valid operating range. 2. jtag inputs do not have a ?ed threshold option and always follow v ccj.
2-25 architecture lattice semiconductor latticexp family data sheet table 2-8. supported output standards hot socketing the latticexp devices have been carefully designed to ensure predictable behavior during power-up and power- down. power supplies can be sequenced in any order. during power up and power-down sequences, the i/os remain in tristate until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within speci?d limits, which allows easy integration with the rest of the system. these capabilities make the latticexp ideal for many multiple power supply and hot-swap applications. sleep mode the latticexp ? devices (v cc = 1.8/2.5/3.3v) have a sleep mode that allows standby current to be reduced by up to three orders of magnitude during periods of system inactivity. entry and exit to sleep mode is controlled by the sleepn pin. during sleep mode, the fpga logic is non-operational, registers and ebr contents are not maintained and i/os are tri-stated. do not enter sleep mode during device programming or con?uration operation. in sleep mode, power supplies can be maintained in their normal operating range, eliminating the need for external switching of power supplies. table 2-9 compares the characteristics of normal, off and sleep modes. output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos18, open drain 4ma, 8ma, 12ma 16ma lvcmos15, open drain 4ma, 8ma lvcmos12, open drain 2ma. 6ma pci33 n/a 3.3 hstl18 class i, ii, iii n/a 1.8 hstl15 class i, iii n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i n/a 1.8 differential hstl18, class i, ii, iii n/a 1.8 differential hstl15, class i, iii n/a 1.5 lvds n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 1. emulated with external resistors.
2-26 architecture lattice semiconductor latticexp family data sheet table 2-9. characteristics of normal, off and sleep modes sleepn pin characteristics the sleepn pin behaves as an lvcmos input with the voltage standard appropriate to the vcc supply for the device. this pin also has a weak pull-up typically in the order of 10? along with a schmidt trigger and glitch ?ter to prevent false triggering. an external pull-up to v cc is recommended when sleep mode is not used to ensure the device stays in normal operation mode. typically the device enters sleep mode several hundred ns after sleepn is held at a valid low and restarts normal operation as speci?d in the sleep mode timing table. the ac and dc speci?ations portion of this data sheet show a detailed timing diagram. con?uration and testing the following section describes the con?uration and testing features of the latticexp family of devices. ieee 1149.1-compliant boundary scan testability all latticexp devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri?ation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device con?uration all latticexp devices contain two possible ports that can be used for device con?uration and programming. the test access port (tap), which supports serial con?uration, and the sysconfig port that supports both byte-wide and serial con?uration. the non-volatile memory in the latticexp can be con?ured in three different modes: in sysconfig mode via the sysconfig port. note this can also be done in background mode. in 1532 mode via the 1149.1 port. in background mode via the 1149.1 port. this allows the device to be operated while reprogramming takes place. the sram con?uration memory can be con?ured in three different ways: at power-up via the on-chip non-volatile memory. in 1532 mode via the 1149.1 port sram direct con?uration. in sysconfig mode via the sysconfig port sram direct con?uration. characteristic normal off sleep sleepn pin high low static icc typical <100ma 0 typical <100ua i/o leakage <10? <1ma <10? power supplies vcc/vccio/vccaux normal range off normal range logic operation user de?ed non operational non operational i/o operation user de?ed tri-state tri-state jtag and programming circuitry operational non-operational non-operational ebr contents and registers maintained non-maintained non-maintained
2-27 architecture lattice semiconductor latticexp family data sheet figure 2-29 provides a pictorial representation of the different programming ports and modes available in the lat- ticexp devices. on power-up, the fpga sram is ready to be con?ured with the sysconfig port active. the ieee 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the tap port. leave alone i/o when using 1532 mode for non-volatile memory programming, users may specify i/os as high, low, tristated or held at current value. this provides excellent ?xibility for implementing systems where reprogramming occurs on- the-?. transfr (t rans parent f ield r econ?uration) transfr (tfr) is a unique lattice technology that allows users to update their logic in the ?ld without interrupting system operation using a single ispvm command. see lattice technical note #tn1087, minimizing system inter- ruption during con?uration using transfr technology, for details. security the latticexp devices contain security bits that, when set, prevent the readback of the sram con?uration and non-volatile memory spaces. once set, the only way to clear security bits is to erase the memory space. for more information on device con?uration, please see details of additional technical documentation at the end of this data sheet. figure 2-29. ispxp block diagram internal logic analyzer capability (isptracy) all latticexp devices support an internal logic analyzer diagnostic feature. the diagnostic features provide capabil- ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem- ory. this feature is enabled by lattices isptracy. the isptracy utility is added into the user design at compile time. for more information on isptracy, please see information regarding additional technical documentation at the end of this data sheet. oscillator every latticexp device has an internal cmos oscillator which is used to derive a master serial clock for con?ura- tion. the oscillator and the master serial clock run continuously in the con?uration mode. the default value of the isp 1149.1 tap port sysconfig peripherial port backgnd 1532 sysconfig sram memory space memory space configure in milliseconds program in seconds download in microseconds power-up refresh port mode memory space
2-28 architecture lattice semiconductor latticexp family data sheet master serial clock is 2.5mhz. table 2-10 lists all the available master serial clock frequencies. when a different master serial clock is selected during the design process, the following sequence takes place: 1. user selects a different master serial clock frequency for con?uration. 2. during con?uration the device starts with the default (2.5mhz) master serial clock frequency. 3. the clock con?uration settings are contained in the early con?uration bit stream. 4. the master serial clock frequency changes to the selected frequency once the clock con?uration bits are received. for further information on the use of this oscillator for con?uration, please see details of additional technical docu- mentation at the end of this data sheet. table 2-10. selectable master serial clock (cclk) frequencies during con?uration density shifting the latticexp family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is also possible to shift a lower utilization design tar- geted for a high-density device to a lower density device. however, the exact details of the ?al resource utilization will impact the likely success in each case. cclk (mhz) cclk (mhz) cclk (mhz) 2.5 1 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 10.0 41 1. default
august 2006 data sheet ds1001 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 3-1 ds1001 dc and switching_02.5 recommended operating conditions 3 absolute maximum ratings 1, 2, 3, 4 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions outside of those indicated in the operational sections of this speci?ation is not impl ied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. 4. all chip grounds are connected together to a common package gnd plane. xpe (1.2v) xpc (1.8v/2.5v/3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccp . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccaux . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v i/o tristate voltage applied 5 . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v dedicated input voltage applied 5 . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 4.25v storage temperature (ambient) . . . . . . . . . . . . . . -65 to 150? . . . . . . . . . . . . . . . -65 to 150? junction temp. (tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125? . . . . . . . . . . . . . . . . . . . +125? 5. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc core supply voltage for 1.2v devices 1.14 1.26 v core supply voltage for 1.8v/2.5v/3.3v devices 1.71 3.465 v v ccp supply voltage for pll for 1.2v devices 1.14 1.26 v supply voltage for pll for 1.8v/2.5v/3.3v devices 1.71 3.465 v v ccaux 4 auxiliary supply voltage 3.135 3.465 v v ccio 1, 2 i/o driver supply voltage 1.14 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.14 3.465 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 c t jflashcom junction temperature, flash programming, commercial 0 85 c t jflashind junction temperature, flash programming, industrial 0 85 c 1. if v ccio or v ccj is set to 3.3v, they must be connected to the same power supply as v ccaux. for the xpe devices (1.2v v cc ), if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc . 2. see recommended voltages by i/o standard in subsequent table. 3. the system designer must ensure that the fpga design stays within the speci?d junction temperature and package thermal capab ilities of the device based on the expected operating frequency, activity factor and environment conditions of the system. 4. v ccaux ramp rate must not exceed 30mv/? during power up when transitioning between 0v and 3.3v. latticexp family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor latticexp family data sheet hot socketing speci?ations 1, 2, 3, 4, 5, 6 1. insensitive to sequence of v cc, v ccaux and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux and v ccio. 2. 0 v cc v cc (max) or 0 v ccaux v ccaux (max). 3. 0 v ccio v ccio (max) for top and bottom i/o banks. 4. 0.2 v ccio v ccio (max) for left and right i/o banks. 5. i dk is additive to i pu, i pw or i bh . 6. lvcmos and lvttl only. symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 v in v ih (max.) +/-1000 ?
3-3 dc and switching characteristics lattice semiconductor latticexp family data sheet dc electrical characteristics over recommended operating conditions supply current (sleep mode) 1, 2, 3 symbol parameter condition min. typ. max. units i il, i ih 1, 2, 4 input or i/o leakage 0 v in (v ccio - 0.2v) 10 ? (v ccio - 0.2v) < v in 3.6v 40 ? i pu i/o active pull-up current 0 v in 0.7 v ccio -30 -150 ? i pd i/o active pull-down current v il (max) v in v ih (max) 30 150 ? i bhls bus hold low sustaining current v in = v il (max) 30 ? i bhhs bus hold high sustaining current v in = 0.7v ccio -30 ? i bhlo bus hold low overdrive current 0 v in v ih (max) 150 ? i bhho bus hold high overdrive current 0 v in v ih (max) -150 ? v bht bus hold trip points 0 v in v ih (max) v il (max) v ih (min) v c1 i/o capacitance 3 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf c2 dedicated input capacitance 3 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. not applicable to sleepn/toe pin. 3. t a 25?, f = 1.0mhz 4. when v ih is higher than v ccio , a transient current typically of 30ns in duration or less with a peak current of 6ma can be expected on the high-to-low transition. symbol parameter device typ. 4 max units i cc core power supply lfxp3c 12 65 ? lfxp6c 14 75 ? lfxp10c 16 85 ? lfxp15c 18 95 ? lfxp20c 20 105 ? i ccp pll power supply (per pll) all lfxp ? devices 1 5 ? i ccaux auxiliary power supply lfxp3c 2 90 a lfxp6c 2 100 ? lfxp10c 2 110 ? lfxp15c 3 120 ? lfxp20c 4 130 ? i ccio bank power supply 5 lfxp3c 2 20 a lfxp6c 2 22 a lfxp10c 2 24 a lfxp15c 3 27 a lfxp20c 4 30 a i ccj vccj power supply all lfxp ? devices 1 5 ? 1. assumes all inputs are con?ured as lvcmos and held at the vccio or gnd. 2. frequency 0mhz. 3. user pattern: blank. 4. t a =25?, power supplies at nominal voltage. 5. per bank.
3-4 dc and switching characteristics lattice semiconductor latticexp family data sheet supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply lfxp3e 15 ma lfxp6e 20 ma lfxp10e 35 ma lfxp15e 45 ma lfxp20e 55 ma lfxp3c 35 ma lfxp6c 40 ma lfxp10c 70 ma lfxp15c 80 ma lfxp20c 90 ma i ccp pll power supply (per pll) all 8 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e/c 22 ma lfxp6e/c 22 ma lfxp10e/c 30 ma lfxp15e/c 30 ma lfxp20e/c 30 ma i ccio bank power supply 6 all 2 ma i ccj v ccj power supply all 1 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the vccio or gnd. 3. frequency 0mhz. 4. user pattern: blank. 5. t a =25?, power supplies at nominal voltage. 6. per bank.
3-5 dc and switching characteristics lattice semiconductor latticexp family data sheet initialization supply current 1, 2, 3, 4, 5, 6 over recommended operating conditions symbol parameter device typ. 7 units i cc core power supply lfxp3e 40 ma lfxp6e 50 ma lfxp10e 110 ma lfxp15e 140 ma lfxp20e 250 ma lfxp3c 60 ma lfxp6c 70 ma lfxp10c 150 ma lfxp15c 180 ma lfxp20c 290 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e /c 50 ma lfxp6e /c 60 ma lfxp10e /c 90 ma lfxp15e /c 110 ma lfxp20e /c 130 ma i ccj v ccj power supply all 2 ma 1. until done signal is active. 2. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 3. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. typical user pattern. 6. assume normal bypass capacitor/decoupling capacitor across the supply. 7. t a =25?, power supplies at nominal voltage.
3-6 dc and switching characteristics lattice semiconductor latticexp family data sheet programming and erase flash supply current 1, 2, 3, 4, 5 symbol parameter device typ .6 units i cc core power supply lfxp3e 30 ma lfxp6e 40 ma lfxp10e 50 ma lfxp15e 60 ma lfxp20e 70 ma lfxp3c 50 ma lfxp6c 60 ma lfxp10c 90 ma lfxp15c 100 ma lfxp20c 110 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e /c 50 ma lfxp6e /c 60 ma lfxp10e /c 90 ma lfxp15e /c 110 ma lfxp20e /c 130 ma i ccj v ccj power supply 7 all 2 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 3. blank user pattern; typical flash pattern. 4. bypass or decoupling capacitor across the supply. 5. jtag programming is at 1mhz. 6. t a =25?, power supplies at nominal voltage. 7. when programming via jtag.
3-7 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio recommended operating conditions v ccio v ref (v) standard min. typ. max. min. typ. max. lvcmos 3.3 3.135 3.3 3.465 lvcmos 2.5 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 1.14 1.2 1.26 lvttl 3.135 3.3 3.465 pci33 3.135 3.3 3.465 sstl18 class i 1.71 1.8 1.89 0.833 0.9 0.969 sstl2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl15 class iii 1.425 1.5 1.575 0.9 hstl 18 class i, ii 1.71 1.8 1.89 0.9 hstl 18 class iii 1.71 1.8 1.89 1.08 lvds 2.375 2.5 2.625 lvpecl 1 3.135 3.3 3.465 blvds 1 2.375 2.5 2.625 1. inputs on chip. outputs are implemented with the addition of external resistors.
3-8 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol (ma) i oh (ma) min. (v) max. (v) min. (v) max. (v) lvcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 hstl15 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8 -8 hstl15 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 9.6 -9.6 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 hstl18 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-9 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio differential electrical characteristics lvds over recommended operating conditions parameter symbol parameter description test conditions min. typ. max. units v inp, v inm input voltage 0 2.4 v v thd differential input threshold +/-100 mv v cm input common mode voltage 100mv v thd v thd /2 1.2 1.8 v 200mv v thd v thd /2 1.2 1.9 v 350mv v thd v thd /2 1.2 2.0 v i in input current power on or power off +/-10 ? v oh output high voltage for v op or v om r t = 100 ohms 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohms 0.9v 1.03 v v od output voltage differential (v op - v om ), r t = 100 ohms 250 350 450 mv v od change in v od between high and low 50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohms 1.125 1.25 1.375 v v os change in v os between h and l 50 mv i osd output short circuit current v od = 0v driver outputs shorted 6ma
3-10 dc and switching characteristics lattice semiconductor latticexp family data sheet differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output classes (class i and class ii) are supported in this mode. lvds25e the top and bottom side of latticexp devices support lvds outputs via emulated complementary lvcmos out- puts in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possi- ble solution for point-to-point signals. figure 3-1. lvds25e output termination example table 3-1. lvds25e dc conditions over recommended operating conditions blvds the latticexp devices support blvds standard. this standard is emulated using complementary lvcmos out- puts in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi- drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. parameter description typical units v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100 i dc dc output current 3.66 ma + - bo u rns cat16-l v 4f12 rs=165 ohms (?%) rs=165 ohms (?%) rd = 140 ohms (?%) rd = 100 ohms (?%) off-chip transmission line, zo = 100 ohm differential v ccio = 2.5 v (?%) v ccio = 2.5 v (?%) o n -chip off-chip o n -chip
3-11 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-2. blvds multi-point output example table 3-2. blvds dc conditions 1 over recommended operating conditions typical symbol description zo = 45 zo = 90 units z out output impedance 100 100 ohms r tleft left end termination 45 90 ohms r tright right end termination 45 90 ohms v oh output high voltage 1.375 1.48 v v ol output low voltage 1.125 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.2 10.2 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + -
3-12 dc and switching characteristics lattice semiconductor latticexp family data sheet lvpecl the latticexp devices support differential lvpecl standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the lvpecl input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-3 is one possible solution for point- to-point signals. figure 3-3. differential lvpecl table 3-3. lvpecl dc conditions 1 over recommended operating conditions for further information on lvpecl, blvds and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. rsds the latticexp devices support differential rsds standard. this standard is emulated using complementary lvc- mos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input standard is sup- ported by the lvds differential input buffer. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-4 are industry standard values for 1 % resistors. symbol description typical units z out output impedance 100 ohms r p driver parallel resistor 187 ohms r s driver series resistor 100 ohms r t receiver termination 100 ohms v oh output high voltage 2.03 v v ol output low voltage 1.27 v v od output differential voltage 0.76 v v cm output common mode voltage 1.65 v z back back impedance 85.7 ohms i dc dc output current 12.7 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential r s = 100 ohms = 100 ohms = 187 ohms = 100 ohms r s r p r t off-chip 3.3v 3.3v + -
3-13 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-4. rsds (reduced swing differential standard) table 3-4. rsds dc conditions parameter description typical units z out output impedance 20 ohms r s driver series resistor 300 ohms r p driver parallel resistor 121 ohms r t receiver termination 100 ohms v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ohms i dc dc output current 3.66 ma r s r s r p r t on-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v zo = 100 + - off-chip
3-14 dc and switching characteristics lattice semiconductor latticexp family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12 ma drive) register to register performance function -5 timing units basic functions 16-bit decoder 6.1 ns 32-bit decoder 7.3 ns 64-bit decoder 8.2 ns 4:1 mux 4.9 ns 8:1 mux 5.3 ns 16:1 mux 5.7 ns 32:1 mux 6.3 ns function -5 timing units basic functions 16-bit decoder 351 mhz 32-bit decoder 248 mhz 64-bit decoder 237 mhz 4:1 mux 590 mhz 8:1 mux 523 mhz 16:1 mux 434 mhz 32:1 mux 355 mhz 8-bit adder 343 mhz 16-bit adder 292 mhz 64-bit adder 130 mhz 16-bit counter 388 mhz 32-bit counter 295 mhz 64-bit counter 200 mhz 64-bit accumulator 164 mhz embedded memory functions single port ram 256x36 bits 254 mhz true-dual port ram 512x18 bits 254 mhz distributed memory functions 16x2 sp ram 434 mhz 64x2 sp ram 332 mhz 128x4 sp ram 235 mhz 32x2 pdp ram 322 mhz 64x4 pdp ram 291 mhz 1. these timing numbers were generated using the isplever design tool. exact performance may vary with design and tool version. the tool uses internal parameters that have been characterized but are not tested on every device. timing v.f0.11
3-15 dc and switching characteristics lattice semiconductor latticexp family data sheet derating logic timing logic timing provided in the following sections of this data sheet and in the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best-case process can be much better than the values given in the tables. the isplever design tool from lattice can provide logic timing numbers at a particular temperature and voltage.
3-16 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp external switching characteristics over recommended operating conditions parameter description device -5 -4 -3 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register lfxp3 5.12 6.12 7.43 ns lfxp6 5.30 6.34 7.69 ns lfxp10 5.52 6.60 8.00 ns lfxp15 5.72 6.84 8.29 ns lfxp20 5.97 7.14 8.65 ns t su clock to data setup - pio input register lfxp3 -0.40 -0.28 -0.16 ns lfxp6 -0.33 -0.32 -0.30 ns lfxp10 -0.61 -0.71 -0.81 ns lfxp15 -0.71 -0.77 -0.87 ns lfxp20 -0.95 -1.14 -1.35 ns t h clock to data hold - pio input register lfxp3 2.10 2.50 2.98 ns lfxp6 2.28 2.72 3.24 ns lfxp10 3.02 3.51 3.71 ns lfxp15 2.70 3.22 3.85 ns lfxp20 2.95 3.52 4.21 ns t su_del clock to data setup - pio input register with input data delay lfxp3 2.38 2.49 2.66 ns lfxp6 2.92 3.18 3.42 ns lfxp10 2.72 2.75 2.84 ns lfxp15 2.99 3.13 3.18 ns lfxp20 4.47 4.56 4.80 ns t h_del clock to data hold - pio input register with input data delay lfxp3 -0.70 -0.80 -0.92 ns lfxp6 -0.47 -0.38 -0.31 ns lfxp10 -0.60 -0.47 -0.32 ns lfxp15 -1.05 -0.98 -1.01 ns lfxp20 -0.80 -0.58 -0.31 ns f max_io clock frequency of i/o and pfu register all 400 360 320 mhz ddr i/o pin parameters 2 t dvadq data valid after dqs (ddr read) all 0.19 0.19 0.19 ui t dvedq data hold after dqs (ddr read) all 0.67 0.67 0.67 ui t dqvbs data valid before dqs all 0.20 0.20 0.20 ui t dqvas data valid after dqs all 0.20 0.20 0.20 ui f max_ddr ddr clock frequency all 95 166 95 133 95 100 mhz primary and secondary clocks f max_pri frequency for primary clock tree all 450 412 375 mhz t w_pri clock pulse width for primary clock all 1.19 1.19 1.19 ns t skew_pri primary clock skew within an i/o bank lfxp3/6/10/15 250 300 350 ps lfxp20 300 350 400 ps 1. general timing numbers based on lvcmos 2.5, 12ma. 2. ddr timing numbers based on sstl i/o. timing v.f0.11
3-17 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-5. ddr timings t dqvas t dqvbs dq and dqs write timings t dqs dq dqs dq dvedq t dvadq dq and dqs read timings
3-18 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp internal timing parameters 1 over recommended operating conditions parameter description -5 -4 -3 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) 0.28 0.34 0.40 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) 0.44 0.53 0.63 ns t lsr_pfu set/reset to output of pfu 0.90 1.08 1.29 ns t sum_pfu clock to mux (m0,m1) input setup time 0.13 0.15 0.19 ns t hm_pfu clock to mux (m0,m1) input hold time -0.04 -0.03 -0.03 ns t sud_pfu clock to d input setup time 0.13 0.16 0.19 ns t hd_pfu clock to d input hold time -0.03 -0.02 -0.02 ns t ck2q_pfu clock to q delay, d-type register con?uration 0.40 0.48 0.58 ns t le2q_pfu clock to q delay latch con?uration 0.53 0.64 0.76 ns t ld2q_pfu d to q throughput delay when latch is enabled 0.55 0.66 0.79 ns pfu dual port memory mode timing t coram_pfu clock to output 0.40 0.48 0.58 ns t sudata_pfu data setup time -0.18 -0.14 -0.11 ns t hdata_pfu data hold time 0.28 0.34 0.40 ns t suaddr_pfu address setup time -0.46 -0.37 -0.30 ns t haddr_pfu address hold time 0.71 0.85 1.02 ns t suwren_pfu write/read enable setup time -0.22 -0.17 -0.14 ns t hwren_pfu write/read enable hold time 0.33 0.40 0.48 ns pic timing pio input/output buffer timing t in_pio input buffer delay 0.62 0.72 0.85 ns t out_pio output buffer delay 2.12 2.54 3.05 ns iologic input/output timing t sui_pio input register setup time (data before clock) 1.35 1.83 2.37 ns t hi_pio input register hold time (data after clock) 0.05 0.05 0.05 ns t coo_pio output register clock to output delay 0.36 0.44 0.52 ns t suce_pio input register clock enable setup time -0.09 -0.07 -0.06 ns t hce_pio input register clock enable hold time 0.13 0.16 0.19 ns t sulsr_pio set/reset setup time 0.19 0.23 0.28 ns t hlsr_pio set/reset hold time -0.14 -0.11 -0.09 ns ebr timing t co_ebr clock to output from address or data 4.01 4.81 5.78 ns t coo_ebr clock to output from ebr output register 0.81 0.97 1.17 ns t sudata_ebr setup data to ebr memory -0.26 -0.21 -0.17 ns t hdata_ebr hold data to ebr memory 0.41 0.49 0.59 ns t suaddr_ebr setup address to ebr memory -0.26 -0.21 -0.17 ns t haddr_ebr hold address to ebr memory 0.41 0.49 0.59 ns t suwren_ebr setup write/read enable to ebr memory -0.17 -0.13 -0.11 ns t hwren_ebr hold write/read enable to ebr memory 0.26 0.31 0.37 ns t suce_ebr clock enable setup time to ebr output register 0.19 0.23 0.28 ns t hce_ebr clock enable hold time to ebr output register -0.13 -0.10 -0.08 ns
3-19 dc and switching characteristics lattice semiconductor latticexp family data sheet t rsto_ebr reset to output delay time from ebr output register 1.61 1.94 2.32 ns pll parameters t rstrec reset recovery to rising clock 1.00 1.00 1.00 ns t rstsu reset signal setup time 1.00 1.00 1.00 ns 1. internal parameters are characterized but not tested on every device. timing v.f0.11 latticexp internal timing parameters 1 (continued) over recommended operating conditions parameter description -5 -4 -3 units min. max. min. max. min. max.
3-20 dc and switching characteristics lattice semiconductor latticexp family data sheet timing diagrams pfu timing diagrams figure 3-6. slice single/dual port write cycle timing figure 3-7. slice single /dual port read cycle timing ck d wre d di[1:0] do[1:0] ad ad[3:0] old data wre d do[1:0] ad ad[3:0] old data
3-21 dc and switching characteristics lattice semiconductor latticexp family data sheet ebr memory timing diagrams figure 3-8. read mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. figure 3-9. read mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t access t access t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 d0 d0 doa output is only updated during a read cycle a1 d1 d0 d1 mem(n) data from previous read mem(n) data from previous read dia ada wea csa clka doa doa (registered) t su t h t access t access
3-22 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-10. read before write (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. figure 3-11. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. a0 a1 a0 a1 d0 d1 d2 doa a0 d2 d3 d1 old a0 data old a1 data d0 d1 dia ada wea csa clka t su t h t access t access t access t access t access a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-23 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp family timing adders 1 over recommended operating conditions buffer type description -5 -4 -3 units input adjusters lvds25e lvds 2.5 emulated 0.5 0.5 0.5 ns lvds25 lvds 0.4 0.4 0.4 ns blvds25 blvds 0.5 0.5 0.5 ns lvpecl33 lvpecl 0.6 0.6 0.6 ns hstl18_i hstl_18 class i 0.4 0.4 0.4 ns hstl18_ii hstl_18 class ii 0.4 0.4 0.4 ns hstl18_iii hstl_18 class iii 0.4 0.4 0.4 ns hstl18d_i differential hstl 18 class i 0.4 0.4 0.4 ns hstl18d_ii differential hstl 18 class ii 0.4 0.4 0.4 ns hstl18d_iii differential hstl 18 class iii 0.4 0.4 0.4 ns hstl15_i hstl_15 class i 0.5 0.5 0.5 ns hstl15_iii hstl_15 class iii 0.5 0.5 0.5 ns hstl15d_i differential hstl 15 class i 0.5 0.5 0.5 ns hstl15d_iii differential hstl 15 class iii 0.5 0.5 0.5 ns sstl33_i sstl_3 class i 0.6 0.6 0.6 ns sstl33_ii sstl_3 class ii 0.6 0.6 0.6 ns sstl33d_i differential sstl_3 class i 0.6 0.6 0.6 ns sstl33d_ii differential sstl_3 class ii 0.6 0.6 0.6 ns sstl25_i sstl_2 class i 0.5 0.5 0.5 ns sstl25_ii sstl_2 class ii 0.5 0.5 0.5 ns sstl25d_i differential sstl_2 class i 0.5 0.5 0.5 ns sstl25d_ii differential sstl_2 class ii 0.5 0.5 0.5 ns sstl18_i sstl_18 class i 0.5 0.5 0.5 ns sstl18d_i differential sstl_18 class i 0.5 0.5 0.5 ns lvttl33 lvttl 0.2 0.2 0.2 ns lvcmos33 lvcmos 3.3 0.2 0.2 0.2 ns lvcmos25 lvcmos 2.5 0.0 0.0 0.0 ns lvcmos18 lvcmos 1.8 0.1 0.1 0.1 ns lvcmos15 lvcmos 1.5 0.1 0.1 0.1 ns lvcmos12 lvcmos 1.2 0.1 0.1 0.1 ns pci33 pci 0.2 0.2 0.2 ns output adjusters lvds25e lvds 2.5 emulated 0.3 0.3 0.3 ns lvds25 lvds 2.5 0.3 0.3 0.3 ns blvds25 blvds 2.5 0.3 0.3 0.3 ns lvpecl33 lvpecl 3.3 0.1 0.1 0.1 ns hstl18_i hstl_18 class i 0.1 0.1 0.1 ns hstl18_ii hstl_18 class ii 0.1 0.1 0.1 ns hstl18_iii hstl_18 class iii 0.2 0.2 0.2 ns hstl18d_i differential hstl 18 class i 0.1 0.1 0.1 ns hstl18d_ii differential hstl 18 class ii -0.1 -0.1 -0.1 ns hstl18d_iii differential hstl 18 class iii 0.2 0.2 0.2 ns
3-24 dc and switching characteristics lattice semiconductor latticexp family data sheet hstl15_i hstl_15 class i 0.2 0.2 0.2 ns hstl15_iii hstl_15 class iii 0.2 0.2 0.2 ns hstl15d_i differential hstl 15 class i 0.2 0.2 0.2 ns hstl15d_iii differential hstl 15 class iii 0.2 0.2 0.2 ns sstl33_i sstl_3 class i 0.1 0.1 0.1 ns sstl33_ii sstl_3 class ii 0.3 0.3 0.3 ns sstl33d_i differential sstl_3 class i 0.1 0.1 0.1 ns sstl33d_ii differential sstl_3 class ii 0.3 0.3 0.3 ns sstl25_i sstl_2 class i -0.1 -0.1 -0.1 ns sstl25_ii sstl_2 class ii 0.3 0.3 0.3 ns sstl25d_i differential sstl_2 class i -0.1 -0.1 -0.1 ns sstl25d_ii differential sstl_2 class ii 0.3 0.3 0.3 ns sstl18_i sstl_1.8 class i 0.1 0.1 0.1 ns sstl18d_i differential sstl_1.8 class i 0.1 0.1 0.1 ns lvttl33_4ma lvttl 4ma drive 0.8 0.8 0.8 ns lvttl33_8ma lvttl 8ma drive 0.5 0.5 0.5 ns lvttl33_12ma lvttl 12ma drive 0.3 0.3 0.3 ns lvttl33_16ma lvttl 16ma drive 0.4 0.4 0.4 ns lvttl33_20ma lvttl 20ma drive 0.3 0.3 0.3 ns lvcmos33_2ma lvcmos 3.3 2ma drive 0.8 0.8 0.8 ns lvcmos33_4ma lvcmos 3.3 4ma drive 0.8 0.8 0.8 ns lvcmos33_8ma lvcmos 3.3 8ma drive 0.5 0.5 0.5 ns lvcmos33_12ma lvcmos 3.3 12ma drive 0.3 0.3 0.3 ns lvcmos33_16ma lvcmos 3.3 16ma drive 0.4 0.4 0.4 ns lvcmos33_20ma lvcmos 3.3 20ma drive 0.3 0.3 0.3 ns lvcmos25_2ma lvcmos 2.5 2ma drive 0.7 0.7 0.7 ns lvcmos25_4ma lvcmos 2.5 4ma drive 0.7 0.7 0.7 ns lvcmos25_8ma lvcmos 2.5 8ma drive 0.4 0.4 0.4 ns lvcmos25_12ma lvcmos 2.5 12ma drive 0.0 0.0 0.0 ns lvcmos25_16ma lvcmos 2.5 16ma drive 0.2 0.2 0.2 ns lvcmos25_20ma lvcmos 2.5 20ma drive 0.4 0.4 0.4 ns lvcmos18_2ma lvcmos 1.8 2ma drive 0.6 0.6 0.6 ns lvcmos18_4ma lvcmos 1.8 4ma drive 0.6 0.6 0.6 ns lvcmos18_8ma lvcmos 1.8 8ma drive 0.4 0.4 0.4 ns lvcmos18_12ma lvcmos 1.8 12ma drive 0.2 0.2 0.2 ns lvcmos18_16ma lvcmos 1.8 16ma drive 0.2 0.2 0.2 ns lvcmos15_2ma lvcmos 1.5 2ma drive 0.6 0.6 0.6 ns lvcmos15_4ma lvcmos 1.5 4ma drive 0.6 0.6 0.6 ns lvcmos15_8ma lvcmos 1.5 8ma drive 0.2 0.2 0.2 ns lvcmos12_2ma lvcmos 1.2 2ma drive 0.4 0.4 0.4 ns lvcmos12_6ma lvcmos 1.2 6ma drive 0.4 0.4 0.4 ns pci33 pci33 0.3 0.3 0.3 ns 1. general timing numbers based on lvcmos 2.5, 12ma. timing v.f0.11 latticexp family timing adders 1 (continued) over recommended operating conditions buffer type description -5 -4 -3 units
3-25 dc and switching characteristics lattice semiconductor latticexp family data sheet sysclock pll timing over recommended operating conditions latticexp ? sleep mode timing parameter descriptions conditions min. typ. max. units f in input clock frequency (clki, clkfb) 25 375 mhz f out output clock frequency (clkop, clkos) 25 375 mhz f out2 k-divider output frequency (clkok) 0.195 187.5 mhz f vco pll vco frequency 375 750 mhz f pfd phase detector input frequency 25 mhz ac characteristics t dt output clock duty cycle default duty cycle elected 3 45 50 55 % t ph 4 output phase accuracy 0.05 ui t opjit 1 output clock period jitter f out 100mhz +/- 125 ps f out < 100mhz 0.02 uipp t sk input clock to output clock skew divider ratio = integer +/- 200 ps t w output clock pulse width at 90 % or 10 % 3 1ns t lock 2 pll lock-in time 150 us t pa programmable delay unit 100 250 400 ps t ipjit input clock period jitter +/- 200 ps t fbkdly external feedback delay 10 ns t hi input clock high time 90 % to 90 % 0.5 ns t lo input clock low time 10 % to 10 % 0.5 ns t rst rst pulse width 10 ns 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. as compared to clkop output. timing v.f0.11 parameter descriptions min. typ. max. units t pwrdn sleepn low to i/o tristate 20 32 ns t pwrup sleepn high to power up lfxp3 1.4 2.1 ms lfxp6 1.7 2.4 ms lfxp10 1.1 1.8 ms lfxp15 1.4 2.1 ms lfxp20 1.7 2.4 ms t wsleepn sleepn pulse width to initiate sleep mode 400 ns t wawake sleepn pulse rejection 120 ns sleepn t pwrup sleep mode t pwrdn i/o
3-26 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp sysconfig port timing speci?ations over recommended operating conditions parameter description min. max. units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 7 ns t hcbdi byte d[0:7] hold time to cclk 3 ns t codo clock to dout in flowthrough mode 12 ns t sucs cs[0:1] setup time to cclk 7 ns t hcs cs[0:1] hold time to cclk 2 ns t suwd write signal setup time to cclk 7 ns t hwd write signal hold time to cclk 2 ns t dcb cclk to busy delay time 12 ns t cord clock to out for read data 12 ns sysconfig byte slave clocking t bsch byte slave clock minimum high pulse 6 ns t bscl byte slave clock minimum low pulse 8 ns t bscyc byte slave clock cycle time 15 ns sysconfig serial (bit) data flow t suscdi di (data in) setup time to cclk 7 ns t hscdi di (data in) hold time to cclk 2 ns t codo clock to dout in flowthrough mode 12 ns sysconfig serial slave clocking t ssch serial slave clock minimum high pulse 6 ns t sscl serial slave clock minimum low pulse 6 ns sysconfig por, initialization and wake up t icfg minimum vcc to init high 50 ms t vmc time from t icfg to valid master clock 2 us t prgmrj program pin pulse rejection 7 ns t prgm 2 programn low time to start con?uration 25 ns t dinit init low time 1 ms t dppinit delay time from programn low to init low 37 ns t dinitd delay time from programn low to done low 37 ns t iodiss user i/o disable from programn low 25 ns t ioenss user i/o enabled time from cclk edge during wake-up sequence 25 ns t mwc additional wake master clock signals after done pin high 120 cycles con?uration master clock (cclk) frequency 1 selected value - 30 % selected value + 30 % mhz duty cycle 40 60 % 1. see table 2-10 for available cclk frequencies. 2. the threshold level for programn, as well as for cfg[1] and cfg[0], is determined by v cc , such that the threshold = v cc /2. timing v.f0.11
3-27 dc and switching characteristics lattice semiconductor latticexp family data sheet flash download time jtag port timing speci?ations over recommended operating conditions symbol parameter min. typ. max. units t refresh programn low-to- high. transition to done high. lfxp3 1.1 1.7 ms lfxp6 1.4 2.0 ms lfxp10 0.9 1.5 ms lfxp15 1.1 1.7 ms lfxp20 1.3 1.9 ms symbol parameter min. max. units f max 25 mhz t btcp tck [bscan] clock pulse width 40 ns t btcph tck [bscan] clock pulse width high 20 ns t btcpl tck [bscan] clock pulse width low 20 ns t bts tck [bscan] setup time 10 ns t bth tck [bscan] hold time 8 ns t btrf tck [bscan] rise/fall time 50 ns t btco tap controller falling edge of clock to valid output 10 ns t btcodis tap controller falling edge of clock to valid disable 10 ns t btcoen tap controller falling edge of clock to valid enable 10 ns t btcrs bscan test capture register setup time 8 ns t btcrh bscan test capture register hold time 25 ns t butco bscan test update register, falling edge of clock to valid output 25 ns t btuodis bscan test update register, falling edge of clock to valid disable 25 ns t btupoen bscan test update register, falling edge of clock to valid enable 25 ns timing v.f0.11
3-28 dc and switching characteristics lattice semiconductor latticexp family data sheet switching test conditions figure 3-12 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, voltage, and other test conditions are shown in figure 3-5. figure 3-12. output test load, lvttl and lvcmos standards table 3-5. test fixture required components, non-terminated interfaces test condition r 1 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) 0pf lvcmos 3.3 = 1.5v lvcmos 2.5 = v ccio /2 lvcmos 1.8 = v ccio /2 lvcmos 1.5 = v ccio /2 lvcmos 1.2 = v ccio /2 lvcmos 2.5 i/o (z -> h) 188 0pf v ccio /2 v ol lvcmos 2.5 i/o (z -> l) v ccio /2 v oh lvcmos 2.5 i/o (h -> z) v oh - 0.15 v ol lvcmos 2.5 i/o (l -> z) v ol + 0.15 v oh note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 cl test poi nt
april 2006 data sheet ds1001 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 4-1 ds1001 pinouts_02.4 signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user programmable pins are shared with special function pins. these pin when not used as special purpose pins can be programmed as i/os for user logic. during con?uration, the user-programmable i/os are tri-stated with an inter- nal pull-up resistor enabled. if any pin is not used (or not bonded to a pack- age pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. gsrn i global reset signal. (active low). any i/o pin can be con?ured to be gsrn. nc no connect. gnd gnd - ground. dedicated pins. v cc vcc - the power supply pins for core logic. dedicated pins. v ccaux v ccaux - the auxiliary power supply pin. it powers all the differential and ref- erenced input buffers. dedicated pins. v ccp0 voltage supply pins for ulm0pll (and llm1pll 1 ). v ccp1 voltage supply pins for urm0pll (and lrm1pll 1 ). gndp0 ground pins for ulm0pll (and llm1pll 1 ). gndp1 ground pins for urm0pll (and lrm1pll 1 ). v cciox ? ccio - the power supply pins for i/o bank x. dedicated pins. v ref1(x), v ref2(x) reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. when not used, they may be used as i/o pins. pll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_pll[t, c]_in_a reference clock (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a, b, c...at each side. [loc][num]_pll[t, c]_fb_a optional feedback (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a, b, c...at each side. pclk[t, c]_[n:0]_[3:0] primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1, 2, 3 within bank. [loc]dqs[num] dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be con?ured to be dqs output. latticexp family data sheet pinout information
4-2 pinout information lattice semiconductor latticexp family data sheet test and programming (dedicated pins. pull-up is enabled on input pins during con?uration.) tms i test mode select input, used to control the 1149.1 state machine. tck i test clock input pin, used to clock the 1149.1 state machine. tdi i test data in pin, used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for con?uration by sending appropriate command. (note: once a con?uration port is selected it is locked. another con?uration port cannot be selected until the power-up sequence). tdo o output pin -test data out pin used to shift data out of device using 1149.1. v ccj ? ccj - the power supply pin for jtag test access port. con?uration pads (used during sysconfig) cfg[1:0] i mode pins used to specify con?uration modes values latched on rising edge of initn. during con?uration, a pull-up is enabled. initn i/o open drain pin - indicates the fpga is ready to be con?ured. during con- ?uration, a pull-up is enabled. if cfg1 and cfg0 are high (sdm) then this pin is pulled low. programn i initiates con?uration sequence when asserted low. this pin always has an active pull-up. done i/o open drain pin - indicates that the con?uration sequence is complete, and the startup sequence is in progress. cclk i/o con?uration clock for con?uring an fpga in sysconfig mode. busy i/o generally not used. after con?uration it is a user-programmable i/o pin. csn i sysconfig chip select (active low). during con?uration, a pull-up is enabled. after con?uration it is user a programmable i/o pin. cs1n i sysconfig chip select (active low). during con?uration, a pull-up is enabled. after con?uration it is user programmable i/o pin writen i write data on parallel port (active low). after con?uration it is a user pro- grammable i/o pin d[7:0] i/o sysconfig port data i/o. after con?uration these are user programmable i/o pins. dout, cson o output for serial con?uration data (rising edge of cclk) when using sysconfig port. after con?uration, it is a user-programmable i/o pin. di i input for serial con?uration data (clocked with cclk) when using syscon- fig port. during con?uration, a pull-up is enabled. after con?uration it is a user-programmable i/o pin. sleepn 2 i sleep mode pin - active low sleep pin. when this pin is held high, the device operates normally. when driven low, the device moves into sleep mode after a speci?d time.this pin has a weak internal pull-up, but when not used an external pull-up to v cc is recommended. toe 3 i test output enable tri-states all i/o pins when driven low. this pin has a weak internal pull-up, but when not used an external pull-up to v cc is recom- mended. 1. applies to lfxp10, lfxp15 and lfxp20 only. 2. applies to lfxp ? devices only. 3. applies to lfxp ? devices only. signal descriptions (cont.) signal name i/o descriptions
4-3 pinout information lattice semiconductor latticexp family data sheet pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic polarity ddr strobe (dqs) and data (dq) pins p[edge] [n-4] atruedq b complement dq p[edge] [n-3] atruedq b complement dq p[edge] [n-2] atruedq b complement dq p[edge] [n-1] atruedq p[edge] [n] b complement dq p[edge] [n+1] a true [edge]dqsn b complement dq p[edge] [n+2] atruedq b complement dq p[edge] [n+3] atruedq b complement dq notes: 1. ? is a row/column pic number. 2. the ddr interface is designed for memories that support one dqs strobe per eight bits of data. in some packages, all the pote ntial ddr data (dq) pins may not be available. 3. the de?ition of the pic numbering is provided in the signal names column of the signal descriptions table in this data sheet .
4-4 pinout information lattice semiconductor latticexp family data sheet pin information summary 1 xp3 xp6 pin type 100 tqfp 144 tqfp 208 pqfp 144 tqfp 208 pqfp 256 fpbga single ended user i/o 62 100 136 100 142 188 differential pair user i/o 2 19 35 56 35 58 80 con?uration dedicated 11 11 11 11 11 11 muxed 14 14 14 14 14 14 tap 555555 dedicated (total without supplies) 666666 v cc 248488 v ccaux 222224 v ccpll 222222 v ccio bank0 112122 bank1 112122 bank2 112122 bank3 112122 bank4 122222 bank5 112122 bank6 112122 bank7 112122 gnd 10 13 24 13 24 24 gnd pll 222222 nc 006000 single ended/differential i/o per bank 2 bank0 8/2 12/3 20/8 12/3 20/8 26/11 bank1 9/0 12/2 18/6 12/2 18/6 26/11 bank2 8/3 12/5 14/6 12/5 17/7 21/9 bank3 6/2 13/5 14/6 13/5 14/6 21/9 bank4 5/2 14/6 21/9 14/6 21/9 26/11 bank5 12/4 12/4 21/9 12/4 21/9 26/11 bank6 4/2 13/5 14/6 13/5 17/7 21/9 bank7 10/4 12/5 14/6 12/5 14/6 21/9 v ccj 111111 1. during con?uration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not u sed (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. 2. the differential i/o per bank includes both dedicated lvds and emulated lvds pin pairs. please see the logic signal connectio ns table for more information.
4-5 pinout information lattice semiconductor latticexp family data sheet pin information summary 1 (cont.) xp10 xp15 xp20 pin type 256 fpbga 388 fpbga 256 fpbga 388 fpbga 484 fpbga 256 fpbga 388 fpbga 484 fpbga single ended user i/o 188 244 188 268 300 188 268 340 differential pair user i/o 2 76 104 76 112 128 76 112 144 con?uration dedicated 11 11 11 11 11 11 11 11 muxed 14 14 14 14 14 14 14 14 tap 55555555 dedicated (total without supplies) 66666666 v cc 8148142881428 v ccaux 4444124412 v ccpll 22222222 v ccio bank0 25254254 bank1 25254254 bank2 24244244 bank3 24244244 bank4 25254254 bank5 25254254 bank6 24244244 bank7 24244244 gnd 24 50 24 50 56 24 50 56 gnd pll 22222222 nc 0240 0400 0 0 single ended/ differential i/o per bank 2 bank0 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank1 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank2 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank3 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank4 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank5 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank6 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank7 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 v ccj 11111111 1. during con?uration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not u sed (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. 2. the differential i/o per bank includes both dedicated lvds and emulated lvds pin pairs. please see the logic signal connectio ns table for more information.
4-6 pinout information lattice semiconductor latticexp family data sheet power supply and nc connections signals 100 tqfp 144 tqfp 208 pqfp 256 fpbga 388 fpbga 484 fpbga v cc 28, 77 14, 39, 73, 112 19, 35, 53, 80, 107, 151, 158, 182 d4, d13, e5, e12, m5, m12, n4, n13 h9, j8, j15, k8, k15, l8, l15, m8, m15, n8, n15, p8, p15, r9 f10, f13, g9, g10, g13, g14, h8, h15, j7, j16, k6, k7, k16, k17, n6, n7, n16, n17, p7, p16, r8, r15, t9, t10, t13, t14, u10, u13 v ccio0 94 133 189, 199 f7, f8 g8, g9, g10, g11, h8 f11, g11, h10, h11 v ccio1 82 119 167, 177 f9, f10 g12, g13, g14, g15, h15 f12, g12, h12, h13 v ccio2 65 98 140, 149 g11, h11 h16, j16, k16, l16 k15, l15, l16, l17 v ccio3 58 88 115, 125 j11, k11 m16, n16, p16, r16 m15, m16, m17, n15 v ccio4 47 61, 68 87, 97 l9, l10 r15, t12, t13, t14, t15 r12, r13, t12, u12 v ccio5 38 49 64, 74 l7, l8 r8, t8, t9, t10, t11 r10, r11, t11, u11 v ccio6 22 21 28, 41 j6, k6 m7, n7, p7, r7 m6, m7, m8, n8 v ccio7 7 8 13, 23 g6, h6 h7, j7, k7, l7 k8, l6, l7, l8 v ccj 73 108 154 d16 e20 e20 v ccp0 17 19 25 h4 m2 l5 v ccp1 60 91 128 j12 m21 l18 v ccaux 25, 71 36, 106 50, 152 e4, e13, m4, m13 g7, g16, t7, t16 g7, g8, g15, g16, h7, h16, r7, r16, t7, t8, t15, t16 gnd 1 10, 18, 21, 33, 43, 44, 52, 59, 68, 84, 90, 99 3, 11, 20, 28, 44, 54, 56, 64, 75, 85, 90, 101, 121, 127, 136 5, 7, 16, 26, 38, 47, 49, 59, 69, 79, 82, 92, 106, 109, 118, 121, 127, 130, 135, 143, 163, 172, 181, 184, 194, 207 a1, a16, f6, f11, g7, g8, g9, g10, h5, h7, h8, h9, h10, j7, j8, j9, j10, j13, k7, k8, k9, k10, l6, l11, t1, t16 a1, a22, h10, h11, h12, h13, h14, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n1, n9, n10, n11, n12, n13, n14, n22, p9, p10, p11, p12, p13, p14, r10, r11, r12, r13, r14, ab1, ab22 a1, a2, a21, a22, b1, b22, h9, h14, j8, j9, j10, j11, j12, j13, j14, j15, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, m20, n2, n9, n10, n11, n12, n13, n14, p8, p9, p10, p11, p12, p13, p14, p15, r9, r14, aa1, aa22, ab1, ab2, ab21, ab22 nc 2 xp3: 27, 33, 34, 129, 133, 134 xp10: c2, c15, c16, c17, d4, d5, d6, d7, d16, d17, e4, e19, w3, w4, w7, w17, w18, w19, w20, y3, y15, y16, aa1, aa2 xp15: b21, c4, c5, c6, c18, c19, c20, c21, d6, d18, e4, e6, e18, f6, l1, l19, l20, m1, m2, m19, m21, n1, n21, n22, p1, p2, u5, u6, u17, u18, v5, v6, v17, v18, w17, w18, w19, y3, y4, y5 1. all grounds must be electrically connected at the board level. 2. nc pins should not be connected to any active signals, v cc or gnd.
4-7 pinout information lattice semiconductor latticexp family data sheet lfxp3 logic signal connections: 100 tqfp pin number pin function bank differential dual function 1 cfg1 0 - - 2 done 0 - - 3 programn 7 - - 4 cclk 7 - - 5 pl3a 7 t lum0_pllt_fb_a 6 pl3b 7 c lum0_pllc_fb_a 7 vccio7 7 - - 8 pl5a 7 - vref1_7 9 pl6b 7 - vref2_7 10 gndio7 7 - - 11 pl7a 7 t 3 dqs 12 pl7b 7 c 3 - 13 pl8a 7 t lum0_pllt_in_a 14 pl8b 7 c lum0_pllc_in_a 15 pl9a 7 t 3 - 16 pl9b 7 c 3 - 17 vccp0 - - - 18 gndp0 - - - 19 pl12a 6 t pclkt6_0 20 pl12b 6 c pclkc6_0 21 gndio6 6 - - 22 vccio6 6 - - 23 pl18a 6 t 3 - 24 pl18b 6 c 3 - 25 vccaux - - - 26 sleepn 1 /toe 2 --- 27 initn 5 - - 28 vcc - - - 29 pb2b 5 - vref1_5 30 pb5b 5 - vref2_5 31 pb8a 5 t - 32 pb8b 5 c - 33 gndio5 5 - - 34 pb9a 5 - - 35 pb10b 5 - - 36 pb11a 5 t dqs 37 pb11b 5 c - 38 vccio5 5 - - 39 pb12a 5 t - 40 pb12b 5 c - 41 pb13a 5 t - 42 pb13b 5 c - 43 gnd - - -
4-8 pinout information lattice semiconductor latticexp family data sheet 44 gndio4 4 - - 45 pb15a 4 t pclkt4_0 46 pb15b 4 c pclkc4_0 47 vccio4 4 - - 48 pb19a 4 t dqs 49 pb19b 4 c vref1_4 50 pb24a 4 - vref2_4 51 pr18b 3 c 3 - 52 gndio3 3 - - 53 pr18a 3 t 3 - 54 pr15b 3 - vref1_3 55 pr14a 3 - vref2_3 56 pr13b 3 c - 57 pr13a 3 t - 58 vccio3 3 - - 59 gndp1 - - - 60 vccp1 - - - 61 pr9b 2 c pclkc2_0 62 pr9a 2 t pclkt2_0 63 pr8b 2 c rum0_pllc_in_a 64 pr8a 2 t rum0_pllt_in_a 65 vccio2 2 - - 66 pr6b 2 - vref1_2 67 pr5a 2 - vref2_2 68 gndio2 2 - - 69 pr3b 2 c rum0_pllc_fb_a 70 pr3a 2 t rum0_pllt_fb_a 71 vccaux - - - 72 tdo - - - 73 vccj - - - 74 tdi - - - 75 tms - - - 76 tck - - - 77 vcc - - - 78 pt24a 1 - - 79 pt23a 1 - d0 80 pt22b 1 - d1 81 pt21a 1 - d2 82 vccio1 1 - - 83 pt20b 1 - d3 84 gndio1 1 - - 85 pt17a 1 - d4 86 pt16a 1 - d5 87 pt15b 1 - d6 lfxp3 logic signal connections: 100 tqfp (cont.) pin number pin function bank differential dual function
4-9 pinout information lattice semiconductor latticexp family data sheet 88 pt14b 1 - d7 89 pt13b 0 c busy 90 gndio0 0 - - 91 pt13a 0 t cs1n 92 pt12b 0 c pclkc0_0 93 pt12a 0 t pclkt0_0 94 vccio0 0 - - 95 pt9a 0 - dout 96 pt8a 0 - writen 97 pt6a 0 - di 98 pt5a 0 - csn 99 gnd - - - 100 cfg0 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 logic signal connections: 100 tqfp (cont.) pin number pin function bank differential dual function
4-10 pinout information lattice semiconductor latticexp family data sheet lfxp3 & lfxp6 logic signal connections: 144 tqfp pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function 1 programn 7 - - programn 7 - - 2 cclk 7 - - cclk 7 - - 3 gnd - - - gnd - -- 4 pl2a 7 t 3 - pl2a 7 t 3 - 5 pl2b 7 c 3 - pl2b 7 c 3 - 6 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a 7 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a 8 vccio7 7 - - vccio7 7 - - 9 pl5a 7 - vref1_7 pl5a 7 - vref1_7 10 pl6b 7 - vref2_7 pl6b 7 - vref2_7 11 gndio7 7 - - gndio7 7 - - 12 pl7a 7 t 3 dqs pl7a 7 t 3 dqs 13 pl7b 7 c 3 - pl7b 7 c 3 - 14 vcc - - - vcc - -- 15 pl8a 7 t lum0_pllt_in_a pl8a 7 t lum0_pllt_in_a 16 pl8b 7 c lum0_pllc_in_a pl8b 7 c lum0_pllc_in_a 17 pl9a 7 t 3 - pl9a 7 t 3 - 18 pl9b 7 c 3 - pl9b 7 c 3 - 19 vccp0 - - - vccp0 - - - 20 gndp0 - - - gndp0 - - - 21 vccio6 6 - - vccio6 6 - - 22 pl11a 6 t 3 - pl16a 6 t 3 - 23 pl11b 6 c 3 - pl16b 6 c 3 - 24 pl12a 6 t pclkt6_0 pl17a 6 t pclkt6_0 25 pl12b 6 c pclkc6_0 pl17b 6 c pclkc6_0 26 pl13a 6 t 3 - pl18a 6 t 3 - 27 pl13b 6 c 3 - pl18b 6 c 3 - 28 gndio6 6 - - gndio6 6 - - 29 pl14a 6 - vref1_6 pl22a 6 - vref1_6 30 pl15b 6 - vref2_6 pl23b 6 - vref2_6 31 pl16a 6 t 3 dqs pl24a 6 t 3 dqs 32 pl16b 6 c 3 - pl24b 6 c 3 - 33 pl17a 6 - - pl25a 6 - - 34 pl18a 6 t 3 - pl26a 6 t 3 - 35 pl18b 6 c 3 - pl26b 6 c 3 - 36 vccaux - - - vccaux - -- 37 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - 38 initn 5 - - initn 5 - - 39 vcc - - - vcc - -- 40 pb2b 5 - vref1_5 pb5b 5 - vref1_5 41 pb5b 5 - vref2_5 pb8b 5 - vref2_5 42 pb7a 5 t - pb10a 5 t - 43 pb7b 5 c - pb10b 5 c - 44 gndio5 5 - - gndio5 5 - - 45 pb9a 5 - - pb12a 5 - - 46 pb10b 5 - - pb13b 5 - -
4-11 pinout information lattice semiconductor latticexp family data sheet 47 pb11a 5 t dqs pb14a 5 t dqs 48 pb11b 5 c - pb14b 5 c - 49 vccio5 5 - - vccio5 5 - - 50 pb12a 5 t - pb15a 5 t - 51 pb12b 5 c - pb15b 5 c - 52 pb13a 5 t - pb16a 5 t - 53 pb13b 5 c - pb16b 5 c - 54 gnd - - - gnd - -- 55 pb14a 4 t - pb17a 4 t - 56 gndio4 4 - - gndio4 4 - - 57 pb14b 4 c - pb17b 4 c - 58 pb15a 4 t pclkt4_0 pb18a 4 t pclkt4_0 59 pb15b 4 c pclkc4_0 pb18b 4 c pclkc4_0 60 pb16a 4 t - pb19a 4 t - 61 vccio4 4 - - vccio4 4 - - 62 pb16b 4 c - pb19b 4 c - 63 pb19a 4 t dqs pb22a 4 t dqs 64 gndio4 4 - - gndio4 4 - - 65 pb19b 4 c vref1_4 pb22b 4 c vref1_4 66 pb20a 4 t - pb23a 4 t - 67 pb20b 4 c - pb23b 4 c - 68 vccio4 4 - - vccio4 4 - - 69 pb22a 4 - - pb25a 4 - - 70 pb24a 4 t vref2_4 pb27a 4 t vref2_4 71 pb24b 4 c - pb27b 4 c - 72 pb25a 4 - - pb28a 4 - - 73 vcc - - - vcc - -- 74 pr18b 3 c 3 - pr26b 3 c 3 - 75 gndio3 3 - - gndio3 3 - - 76 pr18a 3 t 3 - pr26a 3 t 3 - 77 pr17b 3 c - pr25b 3 c - 78 pr17a 3 t - pr25a 3 t - 79 pr16b 3 c 3 - pr24b 3 c 3 - 80 pr16a 3 t 3 dqs pr24a 3 t 3 dqs 81 pr15b 3 - vref1_3 pr23b 3 - vref1_3 82 pr14a 3 - vref2_3 pr22a 3 - vref2_3 83 pr13b 3 c - pr21b 3 c 3 - 84 pr13a 3 t - pr21a 3 t 3 - 85 gnd - - - gnd - -- 86 pr12a 3 - - pr20a 3 - - 87 pr11b 3 c - pr19b 3 c 3 - 88 vccio3 3 - - vccio3 3 - - 89 pr11a 3 t - pr19a 3 t 3 - 90 gndp1 - - - gndp1 - - - 91 vccp1 - - - vccp1 - - - 92 pr9b 2 c pclkc2_0 pr12b 2 c pclkc2_0 lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-12 pinout information lattice semiconductor latticexp family data sheet 93 pr9a 2 t pclkt2_0 pr12a 2 t pclkt2_0 94 pr8b 2 c rum0_pllc_in_a pr8b 2 c rum0_pllc_in_a 95 pr8a 2 t rum0_pllt_in_a pr8a 2 t rum0_pllt_in_a 96 pr7b 2 c 3 - pr7b 2 c 3 - 97 pr7a 2 t 3 dqs pr7a 2 t 3 dqs 98 vccio2 2 - - vccio2 2 - - 99 pr6b 2 - vref1_2 pr6b 2 - vref1_2 100 pr5a 2 - vref2_2 pr5a 2 - vref2_2 101 gndio2 2 - - gndio2 2 - - 102 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a 103 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a 104 pr2b 2 c 3 - pr2b 2 c 3 - 105 pr2a 2 t 3 - pr2a 2 t 3 - 106 vccaux - - - vccaux - -- 107 tdo - - - tdo - - - 108 vccj - - - vccj - -- 109 tdi - - - tdi - -- 110 tms - - - tms - -- 111 tck - - - tck - -- 112 vcc - - - vcc - -- 113 pt25a 1 - vref1_1 pt28a 1 - vref1_1 114 pt24a 1 - - pt27a 1 - - 115 pt23a 1 - d0 pt26a 1 - d0 116 pt22b 1 c d1 pt25b 1 c d1 117 pt22a 1 t vref2_1 pt25a 1 t vref2_1 118 pt21a 1 - d2 pt24a 1 - d2 119 vccio1 1 - - vccio1 1 - - 120 pt20b 1 - d3 pt23b 1 - d3 121 gndio1 1 - - gndio1 1 - - 122 pt17a 1 - d4 pt20a 1 - d4 123 pt16a 1 - d5 pt19a 1 - d5 124 pt15b 1 c d6 pt18b 1 c d6 125 pt15a 1 t - pt18a 1 t - 126 pt14b 1 - d7 pt17b 1 - d7 127 gnd - - - gnd - -- 128 pt13b 0 c busy pt16b 0 c busy 129 pt13a 0 t cs1n pt16a 0 t cs1n 130 pt12b 0 c pclkc0_0 pt15b 0 c pclkc0_0 131 pt12a 0 t pclkt0_0 pt15a 0 t pclkt0_0 132 pt11b 0 c - pt14b 0 c - 133 vccio0 0 - - vccio0 0 - - 134 pt11a 0 t dqs pt14a 0 t dqs 135 pt9a 0 - dout pt12a 0 - dout 136 gndio0 0 - - gndio0 0 - - 137 pt8a 0 - writen pt11a 0 - writen 138 pt7a 0 - vref1_0 pt10a 0 - vref1_0 lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-13 pinout information lattice semiconductor latticexp family data sheet 139 pt6a 0 - di pt9a 0 - di 140 pt5a 0 - csn pt8a 0 - csn 141 pt3b 0 - vref2_0 pt6b 0 - vref2_0 142 cfg0 0 - - cfg0 0 - - 143 cfg1 0 - - cfg1 0 - - 144 done 0 - - done 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-14 pinout information lattice semiconductor latticexp family data sheet lfxp3 & lfxp6 logic signal connections: 208 pqfp pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function 1 cfg1 0 - - cfg1 0 - - 2 done 0 - - done 0 - - 3 programn 7 - - programn 7 - - 4 cclk 7 - - cclk 7 - - 5 gnd - - - gnd - -- 6 pl2a 7 t 3 - pl2a 7 t 3 - 7 gndio7 7 - - gndio7 7 - - 8 pl2b 7 c 3 - pl2b 7 c 3 - 9 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a 10 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a 11 pl4a 7 t 3 - pl4a 7 t 3 - 12 pl4b 7 c 3 - pl4b 7 c 3 - 13 vccio7 7 - - vccio7 7 - - 14 pl5a 7 - vref1_7 pl5a 7 - vref1_7 15 pl6b 7 - vref2_7 pl6b 7 - vref2_7 16 gndio7 7 - - gndio7 7 - - 17 pl7a 7 t 3 dqs pl7a 7 t 3 dqs 18 pl7b 7 c 3 - pl7b 7 c 3 - 19 vcc - - - vcc - -- 20 pl8a 7 t lum0_pllt_in_a pl8a 7 t lum0_pllt_in_a 21 pl8b 7 c lum0_pllc_in_a pl8b 7 c lum0_pllc_in_a 22 pl9a 7 t 3 - pl9a 7 t 3 - 23 vccio7 7 - - vccio7 7 - - 24 pl9b 7 c 3 - pl9b 7 c 3 - 25 vccp0 - - - vccp0 - - - 26 gndp0 - - - gndp0 - - - 27 nc - - - pl15b 6 - - 28 vccio6 6 - - vccio6 6 - - 29 pl11a 6 t 3 - pl16a 6 t 3 - 30 pl11b 6 c 3 - pl16b 6 c 3 - 31 pl12a 6 t pclkt6_0 pl17a 6 t pclkt6_0 32 pl12b 6 c pclkc6_0 pl17b 6 c pclkc6_0 33 nc - - - pl18a 6 t 3 - 34 nc - - - pl18b 6 c 3 - 35 vcc - - - vcc - -- 36 pl13a 6 t 3 - pl21a 6 t 3 - 37 pl13b 6 c 3 - pl21b 6 c 3 - 38 gndio6 6 - - gndio6 6 - - 39 pl14a 6 - vref1_6 pl22a 6 - vref1_6 40 pl15b 6 - vref2_6 pl23b 6 - vref2_6 41 vccio6 6 - - vccio6 6 - - 42 pl16a 6 t 3 dqs pl24a 6 t 3 dqs 43 pl16b 6 c 3 - pl24b 6 c 3 - 44 pl17a 6 t - pl25a 6 t - 45 pl17b 6 c - pl25b 6 c - 46 pl18a 6 t 3 - pl26a 6 t 3 -
4-15 pinout information lattice semiconductor latticexp family data sheet 47 gndio6 6 - - gndio6 6 - - 48 pl18b 6 c 3 - pl26b 6 c 3 - 49 gnd - - - gnd - -- 50 vccaux - - - vccaux - -- 51 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - 52 initn 5 - - initn 5 - - 53 vcc - - - vcc - -- 54 pb2b 5 - vref1_5 pb5b 5 - vref1_5 55 pb3a 5 t - pb6a 5 t dqs 56 pb3b 5 c - pb6b 5 c - 57 pb4a 5 t - pb7a 5 t - 58 pb4b 5 c - pb7b 5 c - 59 gndio5 5 - - gndio5 5 - - 60 pb5a 5 t - pb8a 5 t - 61 pb5b 5 c vref2_5 pb8b 5 c vref2_5 62 pb6a 5 t - pb9a 5 t - 63 pb6b 5 c - pb9b 5 c - 64 vccio5 5 - - vccio5 5 - - 65 pb7a 5 t - pb10a 5 t - 66 pb7b 5 c - pb10b 5 c - 67 pb8a 5 t - pb11a 5 t - 68 pb8b 5 c - pb11b 5 c - 69 gndio5 5 - - gndio5 5 - - 70 pb9a 5 - - pb12a 5 - - 71 pb10b 5 - - pb13b 5 - - 72 pb11a 5 t dqs pb14a 5 t dqs 73 pb11b 5 c - pb14b 5 c - 74 vccio5 5 - - vccio5 5 - - 75 pb12a 5 t - pb15a 5 t - 76 pb12b 5 c - pb15b 5 c - 77 pb13a 5 t - pb16a 5 t - 78 pb13b 5 c - pb16b 5 c - 79 gnd - - - gnd - -- 80 vcc - - - vcc - -- 81 pb14a 4 t - pb17a 4 t - 82 gndio4 4 - - gndio4 4 - - 83 pb14b 4 c - pb17b 4 c - 84 pb15a 4 t pclkt4_0 pb18a 4 t pclkt4_0 85 pb15b 4 c pclkc4_0 pb18b 4 c pclkc4_0 86 pb16a 4 t - pb19a 4 t - 87 vccio4 4 - - vccio4 4 - - 88 pb16b 4 c - pb19b 4 c - 89 pb17a 4 - - pb20a 4 - - 90 pb18b 4 - - pb21b 4 - - 91 pb19a 4 t dqs pb22a 4 t dqs 92 gndio4 4 - - gndio4 4 - - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-16 pinout information lattice semiconductor latticexp family data sheet 93 pb19b 4 c vref1_4 pb22b 4 c vref1_4 94 pb20a 4 t - pb23a 4 t - 95 pb20b 4 c - pb23b 4 c - 96 pb21a 4 t - pb24a 4 t - 97 vccio4 4 - - vccio4 4 - - 98 pb21b 4 c - pb24b 4 c - 99 pb22a 4 t - pb25a 4 t - 100 pb22b 4 c - pb25b 4 c - 101 pb23a 4 t - pb26a 4 t - 102 pb23b 4 c - pb26b 4 c - 103 pb24a 4 t vref2_4 pb27a 4 - vref2_4 104 pb24b 4 c - pb30a 4 t dqs 105 pb25a 4 - - pb30b 4 c - 106 gnd - - - gnd - -- 107 vcc - - - vcc - -- 108 pr18b 3 c 3 - pr26b 3 c 3 - 109 gndio3 3 - - gndio3 3 - - 110 pr18a 3 t 3 - pr26a 3 t 3 - 111 pr17b 3 c - pr25b 3 c - 112 pr17a 3 t - pr25a 3 t - 113 pr16b 3 c 3 - pr24b 3 c 3 - 114 pr16a 3 t 3 dqs pr24a 3 t 3 dqs 115 vccio3 3 - - vccio3 3 - - 116 pr15b 3 - vref1_3 pr23b 3 - vref1_3 117 pr14a 3 - vref2_3 pr22a 3 - vref2_3 118 gndio3 3 - - gndio3 3 - - 119 pr13b 3 c - pr21b 3 c 3 - 120 pr13a 3 t - pr21a 3 t 3 - 121 gnd - - - gnd - -- 122 pr12b 3 c - pr20b 3 c - 123 pr12a 3 t - pr20a 3 t - 124 pr11b 3 c - pr19b 3 c 3 - 125 vccio3 3 - - vccio3 3 - - 126 pr11a 3 t - pr19a 3 t 3 - 127 gndp1 - - - gndp1 - - - 128 vccp1 - - - vccp1 - - - 129 nc - - - pr13a 2 - - 130 gnd - - - gnd - -- 131 pr9b 2 c pclkc2_0 pr12b 2 c pclkc2_0 132 pr9a 2 t pclkt2_0 pr12a 2 t pclkt2_0 133 nc - - - pr11b 2 c 3 - 134 nc - - - pr11a 2 t 3 - 135 gndio2 2 - - gndio2 2 - - 136 pr8b 2 c rum0_pllc_in_a pr8b 2 c rum0_pllc_in_a 137 pr8a 2 t rum0_pllt_in_a pr8a 2 t rum0_pllt_in_a 138 pr7b 2 c 3 - pr7b 2 c 3 - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-17 pinout information lattice semiconductor latticexp family data sheet 139 pr7a 2 t 3 dqs pr7a 2 t 3 dqs 140 vccio2 2 - - vccio2 2 - - 141 pr6b 2 - vref1_2 pr6b 2 - vref1_2 142 pr5a 2 - vref2_2 pr5a 2 - vref2_2 143 gndio2 2 - - gndio2 2 - - 144 pr4b 2 c 3 - pr4b 2 c 3 - 145 pr4a 2 t 3 - pr4a 2 t 3 - 146 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a 147 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a 148 pr2b 2 c 3 - pr2b 2 c 3 - 149 vccio2 2 - - vccio2 2 - - 150 pr2a 2 t 3 - pr2a 2 t 3 - 151 vcc - - - vcc - -- 152 vccaux - - - vccaux - -- 153 tdo - - - tdo - - - 154 vccj - - - vccj - -- 155 tdi - - - tdi - -- 156 tms - - - tms - -- 157 tck - - - tck - -- 158 vcc - - - vcc - -- 159 pt25a 1 - vref1_1 pt28a 1 - vref1_1 160 pt24b 1 c - pt27b 1 c - 161 pt24a 1 t - pt27a 1 t - 162 pt23a 1 - d0 pt26a 1 - d0 163 gndio1 1 - - gndio1 1 - - 164 pt22b 1 c d1 pt25b 1 c d1 165 pt22a 1 t vref2_1 pt25a 1 t vref2_1 166 pt21a 1 - d2 pt24a 1 - d2 167 vccio1 1 - - vccio1 1 - - 168 pt20b 1 c d3 pt23b 1 c d3 169 pt20a 1 t - pt23a 1 t - 170 pt19b 1 c - pt22b 1 c - 171 pt19a 1 t dqs pt22a 1 t dqs 172 gndio1 1 - - gndio1 1 - - 173 pt18b 1 - - pt21b 1 - - 174 pt17a 1 - d4 pt20a 1 - d4 175 pt16b 1 c - pt19b 1 c - 176 pt16a 1 t d5 pt19a 1 t d5 177 vccio1 1 - - vccio1 1 - - 178 pt15b 1 c d6 pt18b 1 c d6 179 pt15a 1 t - pt18a 1 t - 180 pt14b 1 - d7 pt17b 1 - d7 181 gnd - - - gnd - -- 182 vcc - - - vcc - -- 183 pt13b 0 c busy pt16b 0 c busy 184 gndio0 0 - - gndio0 0 - - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-18 pinout information lattice semiconductor latticexp family data sheet 185 pt13a 0 t cs1n pt16a 0 t cs1n 186 pt12b 0 c pclkc0_0 pt15b 0 c pclkc0_0 187 pt12a 0 t pclkt0_0 pt15a 0 t pclkt0_0 188 pt11b 0 c - pt14b 0 c - 189 vccio0 0 - - vccio0 0 - - 190 pt11a 0 t dqs pt14a 0 t dqs 191 pt10b 0 - - pt13b 0 - - 192 pt9a 0 - dout pt12a 0 - dout 193 pt8b 0 c - pt11b 0 c - 194 gndio0 0 - - gndio0 0 - - 195 pt8a 0 t writen pt11a 0 t writen 196 pt7b 0 c - pt10b 0 c - 197 pt7a 0 t vref1_0 pt10a 0 t vref1_0 198 pt6b 0 c - pt9b 0 c - 199 vccio0 0 - - vccio0 0 - - 200 pt6a 0 t di pt9a 0 t di 201 pt5b 0 c - pt8b 0 c - 202 pt5a 0 t csn pt8a 0 t csn 203 pt4b 0 c - pt7b 0 c - 204 pt4a 0 t - pt7a 0 t - 205 pt3b 0 - vref2_0 pt6b 0 - vref2_0 206 pt2b 0 - - pt5b 0 - - 207 gnd - - - gnd - -- 208 cfg0 0 - - cfg0 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-19 pinout information lattice semiconductor latticexp family data sheet lfxp6 & lfxp10 logic signal connections: 256 fpbga ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function c2 programn 7 - - programn 7 - - c1 cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - d2 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a d3 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a d1 pl2a 7 t 3 - pl5a 7 - - e2 pl5a 7 - vref1_7 pl6b 7 - vref1_7 - gndio7 7 - - gndio7 7 - - e1 pl7a 7 t 3 dqs pl7a 7 t 3 dqs f1 pl7b 7 c 3 - pl7b 7 c 3 - e3 pl12a 7 t - pl8a 7 t - f4 pl12b 7 c - pl8b 7 c - f3 pl4a 7 t 3 - pl9a 7 t 3 - f2 pl4b 7 c 3 - pl9b 7 c 3 - - gndio7 7 - - gndio7 7 - - g1 pl2b 7 c 3 - pl11b 7 - - g3 pl8a 7 t lum0_pllt_in_a pl12a 7 t lum0_pllt_in_a g2 pl8b 7 c lum0_pllc_in_a pl12b 7 c lum0_pllc_in_a h1 pl9a 7 t 3 - pl13a 7 t 3 - h2 pl9b 7 c 3 - pl13b 7 c 3 - g4 pl6b 7 - vref2_7 pl14a 7 - vref2_7 g5 pl14a 7 - - pl15b 7 - - - gndio7 7 - - gndio7 7 - - j1 pl11a 7 t 3 - pl16a 7 t 3 dqs j2 pl11b 7 c 3 - pl16b 7 c 3 - h3 pl13a 7 t 3 - pl18a 7 t 3 - j3 pl13b 7 c 3 - pl18b 7 c 3 - h4 vccp0 - - - vccp0 - - - h5 gndp0 - - - gndp0 - - - k1 pl17a 6 t pclkt6_0 pl20a 6 t pclkt6_0 k2 pl17b 6 c pclkc6_0 pl20b 6 c pclkc6_0 - gndio6 6 - - gndio6 6 - - j4 pl15b 6 - - pl22a 6 - - j5 pl22a 6 - vref1_6 pl23b 6 - vref1_6 l1 pl16a 6 t 3 - pl24a 6 t 3 dqs l2 pl16b 6 c 3 - pl24b 6 c 3 - m1 pl18a 6 t 3 - pl25a 6 t llm0_pllt_in_a m2 pl18b 6 c 3 - pl25b 6 c llm0_pllc_in_a k3 pl19a 6 t 3 - pl26a 6 t 3 - - gndio6 6 - - gndio6 6 - - l3 pl19b 6 c 3 - pl26b 6 c 3 - l4 pl21a 6 t 3 - pl28a 6 - -
4-20 pinout information lattice semiconductor latticexp family data sheet k4 pl20a 6 t - pl29a 6 t - k5 pl20b 6 c - pl29b 6 c - - gndio6 6 - - gndio6 6 - - n1 pl23b 6 - vref2_6 pl31a 6 - vref2_6 n2 pl21b 6 c 3 - pl32b 6 - - p1 pl24a 6 t 3 dqs pl33a 6 t 3 dqs p2 pl24b 6 c 3 - pl33b 6 c 3 - l5 pl25a 6 t - pl34a 6 t llm0_pllt_fb_a m6 pl25b 6 c - pl34b 6 c llm0_pllc_fb_a m3 pl26a 6 t 3 - pl35a 6 t 3 - - gndio6 6 - - gndio6 6 - - n3 pl26b 6 c 3 - pl35b 6 c 3 - p4 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - p3 initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - r4 pb2a 5 t - pb6a 5 t - n5 pb2b 5 c - pb6b 5 c - - gndio5 5 - - gndio5 5 - - p5 pb5b 5 - vref1_5 pb7a 5 t vref1_5 r1 pb3b 5 c - pb7b 5 c - n6 pb4a 5 - - pb8a 5 - - m7 pb3a 5 t - pb9b 5 - - r2 pb6a 5 t dqs pb10a 5 t dqs t2 pb6b 5 c - pb10b 5 c - r3 pb7a 5 t - pb11a 5 t - t3 pb7b 5 c - pb11b 5 c - - gndio5 5 - - gndio5 5 - - t4 pb8a 5 t - pb12a 5 t - r5 pb8b 5 c vref2_5 pb12b 5 c vref2_5 n7 pb9a 5 t - pb13a 5 t - m8 pb9b 5 c - pb13b 5 c - t5 pb10a 5 t - pb14a 5 t - p6 pb10b 5 c - pb14b 5 c - t6 pb11a 5 t - pb15a 5 t - r6 pb11b 5 c - pb15b 5 c - - gndio5 5 - - gndio5 5 - - p7 pb12a 5 - - pb16a 5 - - n8 pb13b 5 - - pb17b 5 - - r7 pb14a 5 t dqs pb18a 5 t dqs t7 pb14b 5 c - pb18b 5 c - p8 pb15a 5 t - pb19a 5 t - t8 pb15b 5 c - pb19b 5 c - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-21 pinout information lattice semiconductor latticexp family data sheet r8 pb16a 5 t - pb20a 5 t - t9 pb16b 5 c - pb20b 5 c - r9 pb17a 4 t - pb21a 4 t - - gndio4 4 - - gndio4 4 - - p9 pb17b 4 c - pb21b 4 c - t10 pb18a 4 t pclkt4_0 pb22a 4 t pclkt4_0 t11 pb18b 4 c pclkc4_0 pb22b 4 c pclkc4_0 r10 pb19a 4 t - pb23a 4 t - p10 pb19b 4 c - pb23b 4 c - n9 pb20a 4 - - pb24a 4 - - m9 pb21b 4 - - pb25b 4 - - r12 pb22a 4 t dqs pb26a 4 t dqs - gndio4 4 - - gndio4 4 - - t12 pb22b 4 c vref1_4 pb26b 4 c vref1_4 p13 pb23a 4 t - pb27a 4 t - r13 pb23b 4 c - pb27b 4 c - m11 pb24a 4 t - pb28a 4 t - n11 pb24b 4 c - pb28b 4 c - n10 pb25a 4 t - pb29a 4 t - m10 pb25b 4 c - pb29b 4 c - t13 pb26a 4 t - pb30a 4 t - - gndio4 4 - - gndio4 4 - - p14 pb26b 4 c - pb30b 4 c - r11 pb27a 4 t vref2_4 pb31a 4 t vref2_4 p12 pb27b 4 c - pb31b 4 c - t14 pb28a 4 - - pb32a 4 - - r14 pb29b 4 - - pb33b 4 - - p11 pb30a 4 t dqs pb34a 4 t dqs n12 pb30b 4 c - pb34b 4 c - t15 pb31a 4 t - pb35a 4 t - - gndio4 4 - - gndio4 4 - - r15 pb31b 4 c - pb35b 4 c - - gndio3 3 - - gndio3 3 - - p15 pr26b 3 c 3 - pr34b 3 c rlm0_pllc_fb_a n15 pr26a 3 t 3 - pr34a 3 t rlm0_pllt_fb_a p16 pr24b 3 c 3 - pr33b 3 c 3 - r16 pr24a 3 t 3 dqs pr33a 3 t 3 dqs m15 pr15b 3 - - pr32b 3 - - n14 pr23b 3 - vref1_3 pr31a 3 - vref1_3 - gndio3 3 - - gndio3 3 - - m14 pr25b 3 c - pr29b 3 c - l13 pr25a 3 t - pr29a 3 t - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-22 pinout information lattice semiconductor latticexp family data sheet l15 pr21b 3 c 3 - pr28b 3 c 3 - l14 pr21a 3 t 3 - pr28a 3 t 3 - - gndio3 3 - - gndio3 3 - - l12 pr17b 3 c - pr26a 3 - - m16 pr20b 3 c - pr25b 3 c rlm0_pllc_in_a n16 pr20a 3 t - pr25a 3 t rlm0_pllt_in_a k14 pr19b 3 c 3 - pr24b 3 c 3 - k15 pr19a 3 t 3 - pr24a 3 t 3 dqs k12 pr17a 3 t - pr23b 3 - - k13 pr22a 3 - vref2_3 pr22a 3 - vref2_3 - gndio3 3 - - gndio3 3 - - l16 pr18b 3 c 3 - pr21b 3 c 3 - k16 pr18a 3 t 3 - pr21a 3 t 3 - j15 pr16b 3 c 3 - pr19b 3 c 3 - j14 pr16a 3 t 3 - pr19a 3 t 3 - j13 gndp1 - - - gndp1 - - - j12 vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - j16 pr12b 2 c pclkc2_0 pr17b 2 c pclkc2_0 h16 pr12a 2 t pclkt2_0 pr17a 2 t pclkt2_0 h13 pr13b 2 c 3 - pr16b 2 c 3 - h12 pr13a 2 t 3 - pr16a 2 t 3 dqs h15 pr2b 2 c 3 - pr15b 2 - - h14 pr6b 2 - vref1_2 pr14a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - g15 pr11b 2 c 3 - pr13b 2 c 3 - g14 pr11a 2 t 3 - pr13a 2 t 3 - g16 pr8b 2 c rum0_pllc_in_a pr12b 2 c rum0_pllc_in_a f16 pr8a 2 t rum0_pllt_in_a pr12a 2 t rum0_pllt_in_a g13 pr2a 2 t 3 - pr11b 2 - - - gndio2 2 - - gndio2 2 - - g12 pr9b 2 c 3 - pr8b 2 c - f13 pr9a 2 t 3 - pr8a 2 t - b16 pr7b 2 c 3 - pr7b 2 c 3 - c16 pr7a 2 t 3 dqs pr7a 2 t 3 dqs f15 pr14a 2 - - pr6b 2 - - e15 pr5a 2 - vref2_2 pr5a 2 - vref2_2 - gndio2 2 - - gndio2 2 - - f14 pr4b 2 c 3 - pr4b 2 c 3 - e14 pr4a 2 t 3 - pr4a 2 t 3 - d15 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a c15 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-23 pinout information lattice semiconductor latticexp family data sheet e16 tdo - - - tdo - - - d16 vccj - - - vccj - - - d14 tdi - - - tdi - - - c14 tms - - - tms - - - b14 tck - - - tck - - - - gndio1 1 - - gndio1 1 - - a15 pt31b 1 c - pt35b 1 c - b15 pt31a 1 t - pt35a 1 t - - gndio1 1 - - gndio1 1 - - d12 pt28a 1 - vref1_1 pt34b 1 c vref1_1 c11 pt30a 1 t dqs pt34a 1 t dqs a14 pt29b 1 - - pt33b 1 - - b13 pt30b 1 c - pt32a 1 - - f12 pt27b 1 c - pt31b 1 c - e11 pt27a 1 t - pt31a 1 t - a13 pt26b 1 c - pt30b 1 c - c13 pt26a 1 t d0 pt30a 1 t d0 - gndio1 1 - - gndio1 1 - - c10 pt25b 1 c d1 pt29b 1 c d1 e10 pt25a 1 t vref2_1 pt29a 1 t vref2_1 a12 pt24b 1 c - pt28b 1 c - b12 pt24a 1 t d2 pt28a 1 t d2 c12 pt23b 1 c d3 pt27b 1 c d3 a11 pt23a 1 t - pt27a 1 t - b11 pt22b 1 c - pt26b 1 c - d11 pt22a 1 t dqs pt26a 1 t dqs - gndio1 1 - - gndio1 1 - - b9 pt21b 1 - - pt25b 1 - - d9 pt20a 1 - d4 pt24a 1 - d4 a10 pt19b 1 c - pt23b 1 c - b10 pt19a 1 t d5 pt23a 1 t d5 d10 pt18b 1 c d6 pt22b 1 c d6 a9 pt18a 1 t - pt22a 1 t - c9 pt17b 1 c d7 pt21b 1 c d7 c8 pt17a 1 t - pt21a 1 t - e9 pt16b 0 c busy pt20b 0 c busy - gndio0 0 - - gndio0 0 - - b8 pt16a 0 t cs1n pt20a 0 t cs1n a8 pt15b 0 c pclkc0_0 pt19b 0 c pclkc0_0 a7 pt15a 0 t pclkt0_0 pt19a 0 t pclkt0_0 b7 pt14b 0 c - pt18b 0 c - c7 pt14a 0 t dqs pt18a 0 t dqs lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-24 pinout information lattice semiconductor latticexp family data sheet e8 pt13b 0 - - pt17b 0 - - d8 pt12a 0 - dout pt16a 0 - dout a6 pt11b 0 c - pt15b 0 c - - gndio0 0 - - gndio0 0 - - c6 pt11a 0 t writen pt15a 0 t writen e7 pt10b 0 c - pt14b 0 c - d7 pt10a 0 t vref1_0 pt14a 0 t vref1_0 a5 pt9b 0 c - pt13b 0 c - b5 pt9a 0 t di pt13a 0 t di a4 pt8b 0 c - pt12b 0 c - b6 pt8a 0 t csn pt12a 0 t csn e6 pt7b 0 c - pt11b 0 c - - gndio0 0 - - gndio0 0 - - d6 pt7a 0 t - pt11a 0 t - d5 pt6b 0 c vref2_0 pt10b 0 c vref2_0 a3 pt6a 0 t dqs pt10a 0 t dqs b3 pt5b 0 - - pt9b 0 - - b2 pt4a 0 - - pt8a 0 - - a2 pt3b 0 c - pt7b 0 c - b1 pt3a 0 t - pt7a 0 t - f5 pt2b 0 c - pt6b 0 c - - gndio0 0 - - gndio0 0 - - c5 pt2a 0 t - pt6a 0 t - c4 cfg0 0 - - cfg0 0 - - b4 cfg1 0 - - cfg1 0 - - c3 done 0 - - done 0 - - a1 gnd - - - gnd - - - a16 gnd - - - gnd - - - f11 gnd - - - gnd - - - f6 gnd - - - gnd - - - g10 gnd - - - gnd - - - g7 gnd - - - gnd - - - g8 gnd - - - gnd - - - g9 gnd - - - gnd - - - h10 gnd - - - gnd - - - h7 gnd - - - gnd - - - h8 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j7 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-25 pinout information lattice semiconductor latticexp family data sheet k10 gnd - - - gnd - - - k7 gnd - - - gnd - - - k8 gnd - - - gnd - - - k9 gnd - - - gnd - - - l11 gnd - - - gnd - - - l6 gnd - - - gnd - - - t1 gnd - - - gnd - - - t16 gnd - - - gnd - - - d13 vcc - - - vcc - - - d4 vcc - - - vcc - - - e12 vcc - - - vcc - - - e5 vcc - - - vcc - - - m12 vcc - - - vcc - - - m5 vcc - - - vcc - - - n13 vcc - - - vcc - - - n4 vcc - - - vcc - - - e13 vccaux - - - vccaux - - - e4 vccaux - - - vccaux - - - m13 vccaux - - - vccaux - - - m4 vccaux - - - vccaux - - - f7 vccio0 0 - - vccio0 0 - - f8 vccio0 0 - - vccio0 0 - - f10 vccio1 1 - - vccio1 1 - - f9 vccio1 1 - - vccio1 1 - - g11 vccio2 2 - - vccio2 2 - - h11 vccio2 2 - - vccio2 2 - - j11 vccio3 3 - - vccio3 3 - - k11 vccio3 3 - - vccio3 3 - - l10 vccio4 4 - - vccio4 4 - - l9 vccio4 4 - - vccio4 4 - - l7 vccio5 5 - - vccio5 5 - - l8 vccio5 5 - - vccio5 5 - - j6 vccio6 6 - - vccio6 6 - - k6 vccio6 6 - - vccio6 6 - - g6 vccio7 7 - - vccio7 7 - - h6 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-26 pinout information lattice semiconductor latticexp family data sheet lfxp15 & lfxp20 logic signal connections: 256 fpbga ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function c2 programn 7 - - programn 7 - - c1 cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - - gndio7 7 - - gndio7 7 - - d2 pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a d3 pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a d1 pl9a 7 - - pl9a 7 - - e2 pl10b 7 - vref1_7 pl10b 7 - vref1_7 e1 pl11a 7 t 3 dqs pl11a 7 t 3 dqs f1 pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - e3 pl12a 7 t - pl12a 7 t - f4 pl12b 7 c - pl12b 7 c - f3 pl13a 7 t 3 - pl13a 7 t 3 - f2 pl13b 7 c 3 - pl13b 7 c 3 - g1 pl15b 7 - - pl15b 7 - - - gndio7 7 - - gndio7 7 - - g3 pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a g2 pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a h1 pl17a 7 t 3 - pl17a 7 t 3 - h2 pl17b 7 c 3 - pl17b 7 c 3 - g4 pl18a 7 - vref2_7 pl18a 7 - vref2_7 g5 pl19b 7 - - pl19b 7 - - j1 pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - j2 pl20b 7 c 3 - pl20b 7 c 3 - h3 pl22a 7 t 3 - pl22a 7 t 3 - j3 pl22b 7 c 3 - pl22b 7 c 3 - h4 vccp0 - - - vccp0 - - - h5 gndp0 - - - gndp0 - - - k1 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - k2 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 j4 pl26a 6 - - pl30a 6 - - j5 pl27b 6 - vref1_6 pl31b 6 - vref1_6 l1 pl28a 6 t 3 dqs pl32a 6 t 3 dqs l2 pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - m1 pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a m2 pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a k3 pl30a 6 t 3 - pl34a 6 t 3 - l3 pl30b 6 c 3 - pl34b 6 c 3 -
4-27 pinout information lattice semiconductor latticexp family data sheet l4 pl32a 6 - - pl36a 6 - - - gndio6 6 - - gndio6 6 - - k4 pl33a 6 t - pl37a 6 t - k5 pl33b 6 c - pl37b 6 c - n1 pl35a 6 - vref2_6 pl39a 6 - vref2_6 n2 pl36b 6 - - pl40b 6 - - p1 pl37a 6 t 3 dqs pl41a 6 t 3 dqs p2 pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - l5 pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a m6 pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a m3 pl39a 6 t 3 - pl43a 6 t 3 - n3 pl39b 6 c 3 - pl43b 6 c 3 - - gndio6 6 - - gndio6 6 - - p4 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - p3 initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - r4 pb11a 5 t - pb15a 5 t - n5 pb11b 5 c - pb15b 5 c - p5 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - r1 pb12b 5 c - pb16b 5 c - n6 pb13a 5 - - pb17a 5 - - m7 pb14b 5 - - pb18b 5 - - r2 pb15a 5 t dqs pb19a 5 t dqs t2 pb15b 5 c - pb19b 5 c - r3 pb16a 5 t - pb20a 5 t - t3 pb16b 5 c - pb20b 5 c - t4 pb17a 5 t - pb21a 5 t - r5 pb17b 5 c vref2_5 pb21b 5 c vref2_5 n7 pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - m8 pb18b 5 c - pb22b 5 c - t5 pb19a 5 t - pb23a 5 t - p6 pb19b 5 c - pb23b 5 c - t6 pb20a 5 t - pb24a 5 t - r6 pb20b 5 c - pb24b 5 c - p7 pb21a 5 - - pb25a 5 - - n8 pb22b 5 - - pb26b 5 - - r7 pb23a 5 t dqs pb27a 5 t dqs lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-28 pinout information lattice semiconductor latticexp family data sheet t7 pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - p8 pb24a 5 t - pb28a 5 t - t8 pb24b 5 c - pb28b 5 c - r8 pb25a 5 t - pb29a 5 t - t9 pb25b 5 c - pb29b 5 c - r9 pb26a 4 t - pb30a 4 t - p9 pb26b 4 c - pb30b 4 c - t10 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 t11 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - r10 pb28a 4 t - pb32a 4 t - p10 pb28b 4 c - pb32b 4 c - n9 pb29a 4 - - pb33a 4 - - m9 pb30b 4 - - pb34b 4 - - r12 pb31a 4 t dqs pb35a 4 t dqs t12 pb31b 4 c vref1_4 pb35b 4 c vref1_4 p13 pb32a 4 t - pb36a 4 t - r13 pb32b 4 c - pb36b 4 c - m11 pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - n11 pb33b 4 c - pb37b 4 c - n10 pb34a 4 t - pb38a 4 t - m10 pb34b 4 c - pb38b 4 c - t13 pb35a 4 t - pb39a 4 t - p14 pb35b 4 c - pb39b 4 c - r11 pb36a 4 t vref2_4 pb40a 4 t vref2_4 p12 pb36b 4 c - pb40b 4 c - t14 pb37a 4 - - pb41a 4 - - r14 pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - p11 pb39a 4 t dqs pb43a 4 t dqs n12 pb39b 4 c - pb43b 4 c - t15 pb40a 4 t - pb44a 4 t - r15 pb40b 4 c - pb44b 4 c - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - - gndio3 3 - - gndio3 3 - - - gndio3 3 - - gndio3 3 - - p15 pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a n15 pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-29 pinout information lattice semiconductor latticexp family data sheet p16 pr37b 3 c 3 - pr41b 3 c 3 - r16 pr37a 3 t 3 dqs pr41a 3 t 3 dqs m15 pr36b 3 - - pr40b 3 - - n14 pr35a 3 - vref1_3 pr39a 3 - vref1_3 - gndio3 3 - - gndio3 3 - - m14 pr33b 3 c - pr37b 3 c - l13 pr33a 3 t - pr37a 3 t - l15 pr32b 3 c 3 - pr36b 3 c 3 - l14 pr32a 3 t 3 - pr36a 3 t 3 - l12 pr30a 3 - - pr34a 3 - - m16 pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a n16 pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - k14 pr28b 3 c 3 - pr32b 3 c 3 - k15 pr28a 3 t 3 dqs pr32a 3 t 3 dqs k12 pr27b 3 - - pr31b 3 - - k13 pr26a 3 - vref2_3 pr30a 3 - vref2_3 l16 pr25b 3 c 3 - pr29b 3 c 3 - k16 pr25a 3 t 3 - pr29a 3 t 3 - - gndio3 3 - - gndio3 3 - - j15 pr23b 3 c 3 - pr27b 3 c 3 - j14 pr23a 3 t 3 - pr27a 3 t 3 - j13 gndp1 - - - gndp1 - - - j12 vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - j16 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 h16 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 h13 pr20b 2 c 3 - pr20b 2 c 3 - h12 pr20a 2 t 3 dqs pr20a 2 t 3 dqs h15 pr19b 2 - - pr19b 2 - - h14 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - g15 pr17b 2 c 3 - pr17b 2 c 3 - g14 pr17a 2 t 3 - pr17a 2 t 3 - g16 pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a f16 pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a g13 pr15b 2 - - pr15b 2 - - - gndio2 2 - - gndio2 2 - - g12 pr12b 2 c - pr12b 2 c - f13 pr12a 2 t - pr12a 2 t - b16 pr11b 2 c 3 - pr11b 2 c 3 - c16 pr11a 2 t 3 dqs pr11a 2 t 3 dqs lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-30 pinout information lattice semiconductor latticexp family data sheet - gndio2 2 - - gndio2 2 - - f15 pr10b 2 - - pr10b 2 - - e15 pr9a 2 - vref2_2 pr9a 2 - vref2_2 f14 pr8b 2 c 3 - pr8b 2 c 3 - e14 pr8a 2 t 3 - pr8a 2 t 3 - d15 pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a c15 pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a - gndio2 2 - - gndio2 2 - - e16 tdo - - - tdo - - - d16 vccj - - - vccj - - - d14 tdi - - - tdi - - - c14 tms - - - tms - - - b14 tck - - - tck - - - - gndio1 1 - - gndio1 1 - - - gndio1 1 - - gndio1 1 - - - gndio1 1 - - gndio1 1 - - a15 pt40b 1 c - pt44b 1 c - b15 pt40a 1 t - pt44a 1 t - d12 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - c11 pt39a 1 t dqs pt43a 1 t dqs a14 pt38b 1 - - pt42b 1 - - b13 pt37a 1 - - pt41a 1 - - f12 pt36b 1 c - pt40b 1 c - e11 pt36a 1 t - pt40a 1 t - a13 pt35b 1 c - pt39b 1 c - c13 pt35a 1 t d0 pt39a 1 t d0 c10 pt34b 1 c d1 pt38b 1 c d1 e10 pt34a 1 t vref2_1 pt38a 1 t vref2_1 a12 pt33b 1 c - pt37b 1 c - b12 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - c12 pt32b 1 c d3 pt36b 1 c d3 a11 pt32a 1 t - pt36a 1 t - b11 pt31b 1 c - pt35b 1 c - d11 pt31a 1 t dqs pt35a 1 t dqs b9 pt30b 1 - - pt34b 1 - - d9 pt29a 1 - d4 pt33a 1 - d4 a10 pt28b 1 c - pt32b 1 c - b10 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - d10 pt27b 1 c d6 pt31b 1 c d6 lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-31 pinout information lattice semiconductor latticexp family data sheet a9 pt27a 1 t - pt31a 1 t - c9 pt26b 1 c d7 pt30b 1 c d7 c8 pt26a 1 t - pt30a 1 t - e9 pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - b8 pt25a 0 t cs1n pt29a 0 t cs1n a8 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 a7 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b7 pt23b 0 c - pt27b 0 c - c7 pt23a 0 t dqs pt27a 0 t dqs e8 pt22b 0 - - pt26b 0 - - d8 pt21a 0 - dout pt25a 0 - dout a6 pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - c6 pt20a 0 t writen pt24a 0 t writen e7 pt19b 0 c - pt23b 0 c - d7 pt19a 0 t vref1_0 pt23a 0 t vref1_0 a5 pt18b 0 c - pt22b 0 c - b5 pt18a 0 t di pt22a 0 t di a4 pt17b 0 c - pt21b 0 c - b6 pt17a 0 t csn pt21a 0 t csn e6 pt16b 0 c - pt20b 0 c - d6 pt16a 0 t - pt20a 0 t - d5 pt15b 0 c vref2_0 pt19b 0 c vref2_0 a3 pt15a 0 t dqs pt19a 0 t dqs b3 pt14b 0 - - pt18b 0 - - b2 pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - a2 pt12b 0 c - pt16b 0 c - b1 pt12a 0 t - pt16a 0 t - f5 pt11b 0 c - pt15b 0 c - c5 pt11a 0 t - pt15a 0 t - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - c4 cfg0 0 - - cfg0 0 - - b4 cfg1 0 - - cfg1 0 - - c3 done 0 - - done 0 - - a1 gnd - - - gnd - - - a16 gnd - - - gnd - - - f11 gnd - - - gnd - - - f6 gnd - - - gnd - - - lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-32 pinout information lattice semiconductor latticexp family data sheet g10 gnd - - - gnd - - - g7 gnd - - - gnd - - - g8 gnd - - - gnd - - - g9 gnd - - - gnd - - - h10 gnd - - - gnd - - - h7 gnd - - - gnd - - - h8 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j7 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - k10 gnd - - - gnd - - - k7 gnd - - - gnd - - - k8 gnd - - - gnd - - - k9 gnd - - - gnd - - - l11 gnd - - - gnd - - - l6 gnd - - - gnd - - - t1 gnd - - - gnd - - - t16 gnd - - - gnd - - - d13 vcc - - - vcc - - - d4 vcc - - - vcc - - - e12 vcc - - - vcc - - - e5 vcc - - - vcc - - - m12 vcc - - - vcc - - - m5 vcc - - - vcc - - - n13 vcc - - - vcc - - - n4 vcc - - - vcc - - - e13 vccaux - - - vccaux - - - e4 vccaux - - - vccaux - - - m13 vccaux - - - vccaux - - - m4 vccaux - - - vccaux - - - f7 vccio0 0 - - vccio0 0 - - f8 vccio0 0 - - vccio0 0 - - f10 vccio1 1 - - vccio1 1 - - f9 vccio1 1 - - vccio1 1 - - g11 vccio2 2 - - vccio2 2 - - h11 vccio2 2 - - vccio2 2 - - j11 vccio3 3 - - vccio3 3 - - k11 vccio3 3 - - vccio3 3 - - l10 vccio4 4 - - vccio4 4 - - l9 vccio4 4 - - vccio4 4 - - lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-33 pinout information lattice semiconductor latticexp family data sheet l7 vccio5 5 - - vccio5 5 - - l8 vccio5 5 - - vccio5 5 - - j6 vccio6 6 - - vccio6 6 - - k6 vccio6 6 - - vccio6 6 - - g6 vccio7 7 - - vccio7 7 - - h6 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-34 pinout information lattice semiconductor latticexp family data sheet lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function f4 programn 7 - - programn 7 - - programn 7 - - g4 cclk 7 - - cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - gndio7 7 - - d2 pl2a 7 t 3 - pl6a 7 t 3 - pl6a 7 t 3 - d1 pl2b 7 c 3 - pl6b 7 c 3 - pl6b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - e2 pl3a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a e3 pl3b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a f3 pl4a 7 t 3 - pl8a 7 t 3 - pl8a 7 t 3 - f2 pl4b 7 c 3 - pl8b 7 c 3 - pl8b 7 c 3 - h4 pl5a 7 - - pl9a 7 - - pl9a 7 - - h3 pl6b 7 - vref1_7 pl10b 7 - vref1_7 pl10b 7 - vref1_7 g3 pl7a 7 t 3 dqs pl11a 7 t 3 dqs pl11a 7 t 3 dqs g2 pl7b 7 c 3 - pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - f1 pl8a 7 t - pl12a 7 t - pl12a 7 t - e1 pl8b 7 c - pl12b 7 c - pl12b 7 c - j4 pl9a 7 t 3 - pl13a 7 t 3 - pl13a 7 t 3 - k4 pl9b 7 c 3 - pl13b 7 c 3 - pl13b 7 c 3 - g1 pl11a 7 t 3 - pl15a 7 t 3 - pl15a 7 t 3 - h2 pl11b 7 c 3 - pl15b 7 c 3 - pl15b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - j2 pl12a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a h1 pl12b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a j1 pl13a 7 t 3 - pl17a 7 t 3 - pl17a 7 t 3 - k2 pl13b 7 c 3 - pl17b 7 c 3 - pl17b 7 c 3 - k3 pl14a 7 - vref2_7 pl18a 7 - vref2_7 pl18a 7 - vref2_7 j3 pl15b 7 - - pl19b 7 - - pl19b 7 - - k1 pl16a 7 t 3 dqs pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - gndio7 7 - - l2 pl16b 7 c 3 - pl20b 7 c 3 - pl20b 7 c 3 - l3 pl17a 7 t - pl21a 7 t - pl21a 7 t - l4 pl17b 7 c - pl21b 7 c - pl21b 7 c - l1 pl18a 7 t 3 - pl22a 7 t 3 - pl22a 7 t 3 - m1 pl18b 7 c 3 - pl22b 7 c 3 - pl22b 7 c 3 - m2 vccp0 - - - vccp0 - - - vccp0 - - - n1 gndp0 - - - gndp0 - - - gndp0 - - - m3 pl19a 6 t 3 - pl23a 6 t 3 - pl27a 6 t 3 - m4 pl19b 6 c 3 - pl23b 6 c 3 - pl27b 6 c 3 - p1 pl20a 6 t pclkt6_0 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - gndio6 6 - - n2 pl20b 6 c pclkc6_0 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 r1 pl21a 6 t 3 - pl25a 6 t 3 - pl29a 6 t 3 - p2 pl21b 6 c 3 - pl25b 6 c 3 - pl29b 6 c 3 - n3 pl22a 6 - - pl26a 6 - - pl30a 6 - - n4 pl23b 6 - vref1_6 pl27b 6 - vref1_6 pl31b 6 - vref1_6 t1 pl24a 6 t 3 dqs pl28a 6 t 3 dqs pl32a 6 t 3 dqs r2 pl24b 6 c 3 - pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - -
4-35 pinout information lattice semiconductor latticexp family data sheet u1 pl25a 6 t llm0_pllt_in_a pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a t2 pl25b 6 c llm0_pllc_in_a pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a v1 pl26a 6 t 3 - pl30a 6 t 3 - pl34a 6 t 3 - u2 pl26b 6 c 3 - pl30b 6 c 3 - pl34b 6 c 3 - w1 pl28a 6 t 3 - pl32a 6 t 3 - pl36a 6 t 3 - v2 pl28b 6 c 3 - pl32b 6 c 3 - pl36b 6 c 3 - - gndio6 6 - - gndio6 - - - gndio6 6 - - p3 pl29a 6 t - pl33a 6 t - pl37a 6 t - p4 pl29b 6 c - pl33b 6 c - pl37b 6 c - y1 pl30a 6 t 3 - pl34a 6 t 3 - pl38a 6 t 3 - w2 pl30b 6 c 3 - pl34b 6 c 3 - pl38b 6 c 3 - r3 pl31a 6 - vref2_6 pl35a 6 - vref2_6 pl39a 6 - vref2_6 r4 pl32b 6 - - pl36b 6 - - pl40b 6 - - t3 pl33a 6 t 3 dqs pl37a 6 t 3 dqs pl41a 6 t 3 dqs t4 pl33b 6 c 3 - pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - - v4 pl34a 6 t llm0_pllt_fb_a pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a v3 pl34b 6 c llm0_pllc_fb_a pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a u4 pl35a 6 t 3 - pl39a 6 t 3 - pl43a 6 t 3 - u3 pl35b 6 c 3 - pl39b 6 c 3 - pl43b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - - w5 sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - y2 initn 5 - - initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - gndio5 5 - - y3 - - - - pb3b 5 - - pb7b 5 - - w3 - - - - pb4a 5 t - pb8a 5 t - w4 - - - - pb4b 5 c - pb8b 5 c - aa2 - - - - pb5a 5 - - pb9a 5 - - aa1 - - - - pb6b 5 - - pb10b 5 - - w6 pb2a 5 - - pb7a 5 t dqs pb11a 5 t dqs w7 - - - - pb7b 5 c - pb11b 5 c - y4 pb3a 5 t - pb8a 5 t - pb12a 5 t - - gndio5 5 - - gndio5 5 - - gndio5 5 - - y5 pb3b 5 c - pb8b 5 c - pb12b 5 c - ab2 pb4a 5 t - pb9a 5 t - pb13a 5 t - aa3 pb4b 5 c - pb9b 5 c - pb13b 5 c - ab3 pb5a 5 t - pb10a 5 t - pb14a 5 t - aa4 pb5b 5 c - pb10b 5 c - pb14b 5 c - w8 pb6a 5 t - pb11a 5 t - pb15a 5 t - w9 pb6b 5 c - pb11b 5 c - pb15b 5 c - ab4 pb7a 5 t vref1_5 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa5 pb7b 5 c - pb12b 5 c - pb16b 5 c - ab5 pb8a 5 - - pb13a 5 - - pb17a 5 - - y6 pb9b 5 - - pb14b 5 - - pb18b 5 - - aa6 pb10a 5 t dqs pb15a 5 t dqs pb19a 5 t dqs ab6 pb10b 5 c - pb15b 5 c - pb19b 5 c - y9 pb11a 5 t - pb16a 5 t - pb20a 5 t - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-36 pinout information lattice semiconductor latticexp family data sheet y10 pb11b 5 c - pb16b 5 c - pb20b 5 c - aa7 pb12a 5 t - pb17a 5 t - pb21a 5 t - ab7 pb12b 5 c vref2_5 pb17b 5 c vref2_5 pb21b 5 c vref2_5 y7 pb13a 5 t - pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa8 pb13b 5 c - pb18b 5 c - pb22b 5 c - ab8 pb14a 5 t - pb19a 5 t - pb23a 5 t - y8 pb14b 5 c - pb19b 5 c - pb23b 5 c - ab9 pb15a 5 t - pb20a 5 t - pb24a 5 t - aa9 pb15b 5 c - pb20b 5 c - pb24b 5 c - w10 pb16a 5 - - pb21a 5 - - pb25a 5 - - w11 pb17b 5 - - pb22b 5 - - pb26b 5 - - ab10 pb18a 5 t dqs pb23a 5 t dqs pb27a 5 t dqs aa10 pb18b 5 c - pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa11 pb19a 5 t - pb24a 5 t - pb28a 5 t - ab11 pb19b 5 c - pb24b 5 c - pb28b 5 c - y11 pb20a 5 t - pb25a 5 t - pb29a 5 t - y12 pb20b 5 c - pb25b 5 c - pb29b 5 c - ab12 pb21a 4 t - pb26a 4 t - pb30a 4 t - aa12 pb21b 4 c - pb26b 4 c - pb30b 4 c - ab13 pb22a 4 t pclkt4_0 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 aa13 pb22b 4 c pclkc4_0 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa14 pb23a 4 t - pb28a 4 t - pb32a 4 t - ab14 pb23b 4 c - pb28b 4 c - pb32b 4 c - w12 pb24a 4 - - pb29a 4 - - pb33a 4 - - w13 pb25b 4 - - pb30b 4 - - pb34b 4 - - aa15 pb26a 4 t dqs pb31a 4 t dqs pb35a 4 t dqs ab15 pb26b 4 c vref1_4 pb31b 4 c vref1_4 pb35b 4 c vref1_4 aa16 pb27a 4 t - pb32a 4 t - pb36a 4 t - ab16 pb27b 4 c - pb32b 4 c - pb36b 4 c - y17 pb28a 4 t - pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa17 pb28b 4 c - pb33b 4 c - pb37b 4 c - y13 pb29a 4 t - pb34a 4 t - pb38a 4 t - y14 pb29b 4 c - pb34b 4 c - pb38b 4 c - ab17 pb30a 4 t - pb35a 4 t - pb39a 4 t - y18 pb30b 4 c - pb35b 4 c - pb39b 4 c - aa18 pb31a 4 t vref2_4 pb36a 4 t vref2_4 pb40a 4 t vref2_4 ab18 pb31b 4 c - pb36b 4 c - pb40b 4 c - y19 pb32a 4 - - pb37a 4 - - pb41a 4 - - ab19 pb33b 4 - - pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa19 pb34a 4 t dqs pb39a 4 t dqs pb43a 4 t dqs y20 pb34b 4 c - pb39b 4 c - pb43b 4 c - w14 pb35a 4 t - pb40a 4 t - pb44a 4 t - w15 pb35b 4 c - pb40b 4 c - pb44b 4 c - ab20 pb36a 4 t - pb41a 4 t - pb45a 4 t - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-37 pinout information lattice semiconductor latticexp family data sheet aa20 pb36b 4 c - pb41b 4 c - pb45b 4 c - ab21 pb37a 4 t - pb42a 4 t - pb46a 4 t - aa21 pb37b 4 c - pb42b 4 c - pb46b 4 c - aa22 pb38a 4 t - pb43a 4 t - pb47a 4 t - y21 pb38b 4 c - pb43b 4 c - pb47b 4 c - - gndio4 4 - - gndio4 4 - - gndio4 4 - - w16 pb39a 4 - - pb44a 4 t - pb48a 4 t - w17 - - - - pb44b 4 c - pb48b 4 c - y15 - - - - pb45a 4 - - pb49a 4 - - y16 - - - - pb46b 4 - - pb50b 4 - - w19 - - - - pb47a 4 t dqs pb51a 4 t dqs w18 - - - - pb47b 4 c - pb51b 4 c - w20 - - - - pb48a 4 - - pb52a 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - - gndio3 3 - - gndio3 3 - - gndio3 3 - - t20 pr35b 3 c 3 - pr39b 3 c 3 - pr43b 3 c 3 - t19 pr35a 3 t 3 - pr39a 3 t 3 - pr43a 3 t 3 - - gndio3 3 - - gndio3 3 - - gndio3 3 - - u19 pr34b 3 c rlm0_pllc_fb_a pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a u20 pr34a 3 t rlm0_pllt_fb_a pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a v19 pr33b 3 c 3 - pr37b 3 c 3 - pr41b 3 c 3 - v20 pr33a 3 t 3 dqs pr37a 3 t 3 dqs pr41a 3 t 3 dqs r19 pr32b 3 - - pr36b 3 - - pr40b 3 - - r20 pr31a 3 - vref1_3 pr35a 3 - vref1_3 pr39a 3 - vref1_3 w21 pr30b 3 c 3 - pr34b 3 c 3 - pr38b 3 c 3 - y22 pr30a 3 t 3 - pr34a 3 t 3 - pr38a 3 t 3 - - gndio3 3 - - gndio3 3 - - gndio3 3 - - p19 pr29b 3 c - pr33b 3 c - pr37b 3 c - p20 pr29a 3 t - pr33a 3 t - pr37a 3 t - v21 pr28b 3 c 3 - pr32b 3 c 3 - pr36b 3 c 3 - w22 pr28a 3 t 3 - pr32a 3 t 3 - pr36a 3 t 3 - u21 pr26b 3 c 3 - pr30b 3 c 3 - pr34b 3 c 3 - v22 pr26a 3 t 3 - pr30a 3 t 3 - pr34a 3 t 3 - t21 pr25b 3 c rlm0_pllc_in_a pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a u22 pr25a 3 t rlm0_pllt_in_a pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - gndio3 3 - - r21 pr24b 3 c 3 - pr28b 3 c 3 - pr32b 3 c 3 - t22 pr24a 3 t 3 dqs pr28a 3 t 3 dqs pr32a 3 t 3 dqs n19 pr23b 3 - - pr27b 3 - - pr31b 3 - - n20 pr22a 3 - vref2_3 pr26a 3 - vref2_3 pr30a 3 - vref2_3 r22 pr21b 3 c 3 - pr25b 3 c 3 - pr29b 3 c 3 - p22 pr21a 3 t 3 - pr25a 3 t 3 - pr29a 3 t 3 - p21 pr20b 3 c - pr24b 3 c - pr28b 3 c - n21 pr20a 3 t - pr24a 3 t - pr28a 3 t - - gndio3 3 - - gndio3 3 - - gndio3 3 - - m20 pr19b 3 c 3 - pr23b 3 c 3 - pr27b 3 c 3 - m19 pr19a 3 t 3 - pr23a 3 t 3 - pr27a 3 t 3 - n22 gndp1 - - - gndp1 - - - gndp1 - - - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-38 pinout information lattice semiconductor latticexp family data sheet m21 vccp1 - - - vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - gndio2 2 - - m22 pr18b 2 c 3 - pr22b 2 c 3 - pr22b 2 c 3 - l22 pr18a 2 t 3 - pr22a 2 t 3 - pr22a 2 t 3 - k22 pr17b 2 c pclkc2_0 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 k21 pr17a 2 t pclkt2_0 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 l19 pr16b 2 c 3 - pr20b 2 c 3 - pr20b 2 c 3 - k20 pr16a 2 t 3 dqs pr20a 2 t 3 dqs pr20a 2 t 3 dqs l20 pr15b 2 - - pr19b 2 - - pr19b 2 - - l21 pr14a 2 - vref1_2 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - gndio2 2 - - j22 pr13b 2 c 3 - pr17b 2 c 3 - pr17b 2 c 3 - j21 pr13a 2 t 3 - pr17a 2 t 3 - pr17a 2 t 3 - h22 pr12b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a h21 pr12a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a k19 pr11b 2 c 3 - pr15b 2 c 3 - pr15b 2 c 3 - j19 pr11a 2 t 3 - pr15a 2 t 3 - pr15a 2 t 3 - - gndio2 2 - - gndio2 2 - - gndio2 2 - - j20 pr9b 2 c 3 - pr13b 2 c 3 - pr13b 2 c 3 - h20 pr9a 2 t 3 - pr13a 2 t 3 - pr13a 2 t 3 - h19 pr8b 2 c - pr12b 2 c - pr12b 2 c - g19 pr8a 2 t - pr12a 2 t - pr12a 2 t - g22 pr7b 2 c 3 - pr11b 2 c 3 - pr11b 2 c 3 - g21 pr7a 2 t 3 dqs pr11a 2 t 3 dqs pr11a 2 t 3 dqs - gndio2 2 - - gndio2 2 - - gndio2 2 - - f20 pr6b 2 - - pr10b 2 - - pr10b 2 - - g20 pr5a 2 - vref2_2 pr9a 2 - vref2_2 pr9a 2 - vref2_2 f22 pr4b 2 c 3 - pr8b 2 c 3 - pr8b 2 c 3 - f21 pr4a 2 t 3 - pr8a 2 t 3 - pr8a 2 t 3 - e22 pr3b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a e21 pr3a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a d22 pr2b 2 c 3 - pr6b 2 c 3 - pr6b 2 c 3 - d21 pr2a 2 t 3 - pr6a 2 t 3 - pr6a 2 t 3 - - gndio2 2 - - gndio2 2 - - gndio2 2 - - f19 tdo - - - tdo - - - tdo - -- e20 vccj - - - vccj - - - vccj - -- d20 tdi - - - tdi - - - tdi - -- d19 tms - - - tms - - - tms - -- d18 tck - - - tck - - - tck - -- - gndio1 1 - - gndio1 1 - - gndio1 1 - - e19 - - - - pt48a 1 - - pt52a 1 - - d17 - - - - pt47b 1 c - pt51b 1 c - d16 - - - - pt47a 1 t dqs pt51a 1 t dqs c16 - - - - pt46b 1 - - pt50b 1 - - c15 - - - - pt45a 1 - - pt49a 1 - - c17 - - - - pt44b 1 c - pt48b 1 c - c18 pt39a 1 - - pt44a 1 t - pt48a 1 t - c19 pt38b 1 c - pt43b 1 c - pt47b 1 c - - gndio1 1 - - gndio1 1 - - gndio1 1 - - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-39 pinout information lattice semiconductor latticexp family data sheet c20 pt38a 1 t - pt43a 1 t - pt47a 1 t - c21 pt37b 1 c - pt42b 1 c - pt46b 1 c - c22 pt37a 1 t - pt42a 1 t - pt46a 1 t - b22 pt36b 1 c - pt41b 1 c - pt45b 1 c - a21 pt36a 1 t - pt41a 1 t - pt45a 1 t - d15 pt35b 1 c - pt40b 1 c - pt44b 1 c - d14 pt35a 1 t - pt40a 1 t - pt44a 1 t - b21 pt34b 1 c vref1_1 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - gndio1 1 - - a20 pt34a 1 t dqs pt39a 1 t dqs pt43a 1 t dqs b20 pt33b 1 - - pt38b 1 - - pt42b 1 - - a19 pt32a 1 - - pt37a 1 - - pt41a 1 - - b19 pt31b 1 c - pt36b 1 c - pt40b 1 c - a18 pt31a 1 t - pt36a 1 t - pt40a 1 t - c14 pt30b 1 c - pt35b 1 c - pt39b 1 c - c13 pt30a 1 t d0 pt35a 1 t d0 pt39a 1 t d0 b18 pt29b 1 c d1 pt34b 1 c d1 pt38b 1 c d1 a17 pt29a 1 t vref2_1 pt34a 1 t vref2_1 pt38a 1 t vref2_1 b17 pt28b 1 c - pt33b 1 c - pt37b 1 c - a16 pt28a 1 t d2 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - gndio1 1 - - b16 pt27b 1 c d3 pt32b 1 c d3 pt36b 1 c d3 a15 pt27a 1 t - pt32a 1 t - pt36a 1 t - b15 pt26b 1 c - pt31b 1 c - pt35b 1 c - a14 pt26a 1 t dqs pt31a 1 t dqs pt35a 1 t dqs d13 pt25b 1 - - pt30b 1 - - pt34b 1 - - d12 pt24a 1 - d4 pt29a 1 - d4 pt33a 1 - d4 b14 pt23b 1 c - pt28b 1 c - pt32b 1 c - a13 pt23a 1 t d5 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - gndio1 1 - - b13 pt22b 1 c d6 pt27b 1 c d6 pt31b 1 c d6 a12 pt22a 1 t - pt27a 1 t - pt31a 1 t - b12 pt21b 1 c d7 pt26b 1 c d7 pt30b 1 c d7 c12 pt21a 1 t - pt26a 1 t - pt30a 1 t - c11 pt20b 0 c busy pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - gndio0 0 - - b11 pt20a 0 t cs1n pt25a 0 t cs1n pt29a 0 t cs1n a11 pt19b 0 c pclkc0_0 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 a10 pt19a 0 t pclkt0_0 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b10 pt18b 0 c - pt23b 0 c - pt27b 0 c - b9 pt18a 0 t dqs pt23a 0 t dqs pt27a 0 t dqs d11 pt17b 0 - - pt22b 0 - - pt26b 0 - - d10 pt16a 0 - dout pt21a 0 - dout pt25a 0 - dout a9 pt15b 0 c - pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c8 pt15a 0 t writen pt20a 0 t writen pt24a 0 t writen b8 pt14b 0 c - pt19b 0 c - pt23b 0 c - a8 pt14a 0 t vref1_0 pt19a 0 t vref1_0 pt23a 0 t vref1_0 c7 pt13b 0 c - pt18b 0 c - pt22b 0 c - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-40 pinout information lattice semiconductor latticexp family data sheet a7 pt13a 0 t di pt18a 0 t di pt22a 0 t di b7 pt12b 0 c - pt17b 0 c - pt21b 0 c - c6 pt12a 0 t csn pt17a 0 t csn pt21a 0 t csn c10 pt11b 0 c - pt16b 0 c - pt20b 0 c - c9 pt11a 0 t - pt16a 0 t - pt20a 0 t - a6 pt10b 0 c vref2_0 pt15b 0 c vref2_0 pt19b 0 c vref2_0 b6 pt10a 0 t dqs pt15a 0 t dqs pt19a 0 t dqs a5 pt9b 0 - - pt14b 0 - - pt18b 0 - - b5 pt8a 0 - - pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c5 pt7b 0 c - pt12b 0 c - pt16b 0 c - a4 pt7a 0 t - pt12a 0 t - pt16a 0 t - d9 pt6b 0 c - pt11b 0 c - pt15b 0 c - d8 pt6a 0 t - pt11a 0 t - pt15a 0 t - b4 pt5b 0 c - pt10b 0 c - pt14b 0 c - a2 pt5a 0 t - pt10a 0 t - pt14a 0 t - a3 pt4b 0 c - pt9b 0 c - pt13b 0 c - b3 pt4a 0 t - pt9a 0 t - pt13a 0 t - c4 pt3b 0 c - pt8b 0 c - pt12b 0 c - c3 pt3a 0 t - pt8a 0 t - pt12a 0 t - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c2 - - - - pt7b 0 c - pt11b 0 c - d3 pt2a 0 - - pt7a 0 t dqs pt11a 0 t dqs d7 - - - - pt6b 0 - - pt10b 0 - - d6 - - - - pt5a 0 - - pt9a 0 - - e4 - - - - pt4b 0 c - pt8b 0 c - d4 - - - - pt4a 0 t - pt8a 0 t - d5 - - - - pt3b 0 - - pt7b 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c1 cfg0 0 - - cfg0 0 - - cfg0 0 - - b2 cfg1 0 - - cfg1 0 - - cfg1 0 - - b1 done 0 - - done 0 - - done 0 - - a1 gnd - - - gnd - - - gnd - - - a22 gnd - - - gnd - - - gnd - - - ab1 gnd - - - gnd - - - gnd - - - ab22 gnd - - - gnd - - - gnd - - - h10 gnd - - - gnd - - - gnd - - - h11 gnd - - - gnd - - - gnd - - - h12 gnd - - - gnd - - - gnd - - - h13 gnd - - - gnd - - - gnd - - - h14 gnd - - - gnd - - - gnd - - - j10 gnd - - - gnd - - - gnd - - - j11 gnd - - - gnd - - - gnd - - - j12 gnd - - - gnd - - - gnd - - - j13 gnd - - - gnd - - - gnd - - - j14 gnd - - - gnd - - - gnd - - - j9 gnd - - - gnd - - - gnd - - - k10 gnd - - - gnd - - - gnd - - - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-41 pinout information lattice semiconductor latticexp family data sheet k11 gnd - - - gnd - - - gnd - - - k12 gnd - - - gnd - - - gnd - - - k13 gnd - - - gnd - - - gnd - - - k14 gnd - - - gnd - - - gnd - - - k9 gnd - - - gnd - - - gnd - - - l10 gnd - - - gnd - - - gnd - - - l11 gnd - - - gnd - - - gnd - - - l12 gnd - - - gnd - - - gnd - - - l13 gnd - - - gnd - - - gnd - - - l14 gnd - - - gnd - - - gnd - - - l9 gnd - - - gnd - - - gnd - - - m10 gnd - - - gnd - - - gnd - - - m11 gnd - - - gnd - - - gnd - - - m12 gnd - - - gnd - - - gnd - - - m13 gnd - - - gnd - - - gnd - - - m14 gnd - - - gnd - - - gnd - - - m9 gnd - - - gnd - - - gnd - - - n10 gnd - - - gnd - - - gnd - - - n11 gnd - - - gnd - - - gnd - - - n12 gnd - - - gnd - - - gnd - - - n13 gnd - - - gnd - - - gnd - - - n14 gnd - - - gnd - - - gnd - - - n9 gnd - - - gnd - - - gnd - - - p10 gnd - - - gnd - - - gnd - - - p11 gnd - - - gnd - - - gnd - - - p12 gnd - - - gnd - - - gnd - - - p13 gnd - - - gnd - - - gnd - - - p14 gnd - - - gnd - - - gnd - - - p9 gnd - - - gnd - - - gnd - - - r10 gnd - - - gnd - - - gnd - - - r11 gnd - - - gnd - - - gnd - - - r12 gnd - - - gnd - - - gnd - - - r13 gnd - - - gnd - - - gnd - - - r14 gnd - - - gnd - - - gnd - - - h9 vcc - - - vcc - - - vcc - - - j15 vcc - - - vcc - - - vcc - - - j8 vcc - - - vcc - - - vcc - - - k15 vcc - - - vcc - - - vcc - - - k8 vcc - - - vcc - - - vcc - - - l15 vcc - - - vcc - - - vcc - - - l8 vcc - - - vcc - - - vcc - - - m15 vcc - - - vcc - - - vcc - - - m8 vcc - - - vcc - - - vcc - - - n15 vcc - - - vcc - - - vcc - - - n8 vcc - - - vcc - - - vcc - - - p15 vcc - - - vcc - - - vcc - - - p8 vcc - - - vcc - - - vcc - - - r9 vcc - - - vcc - - - vcc - - - g16 vccaux - - - vccaux - - - vccaux - - - lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-42 pinout information lattice semiconductor latticexp family data sheet g7 vccaux - - - vccaux - - - vccaux - - - t16 vccaux - - - vccaux - - - vccaux - - - t7 vccaux - - - vccaux - - - vccaux - - - g10 vccio0 0 - - vccio0 0 - - vccio0 0 - - g11 vccio0 0 - - vccio0 0 - - vccio0 0 - - g8 vccio0 0 - - vccio0 0 - - vccio0 0 - - g9 vccio0 0 - - vccio0 0 - - vccio0 0 - - h8 vccio0 0 - - vccio0 0 - - vccio0 0 - - g12 vccio1 1 - - vccio1 1 - - vccio1 1 - - g13 vccio1 1 - - vccio1 1 - - vccio1 1 - - g14 vccio1 1 - - vccio1 1 - - vccio1 1 - - g15 vccio1 1 - - vccio1 1 - - vccio1 1 - - h15 vccio1 1 - - vccio1 1 - - vccio1 1 - - h16 vccio2 2 - - vccio2 2 - - vccio2 2 - - j16 vccio2 2 - - vccio2 2 - - vccio2 2 - - k16 vccio2 2 - - vccio2 2 - - vccio2 2 - - l16 vccio2 2 - - vccio2 2 - - vccio2 2 - - m16 vccio3 3 - - vccio3 3 - - vccio3 3 - - n16 vccio3 3 - - vccio3 3 - - vccio3 3 - - p16 vccio3 3 - - vccio3 3 - - vccio3 3 - - r16 vccio3 3 - - vccio3 3 - - vccio3 3 - - r15 vccio4 4 - - vccio4 4 - - vccio4 4 - - t12 vccio4 4 - - vccio4 4 - - vccio4 4 - - t13 vccio4 4 - - vccio4 4 - - vccio4 4 - - t14 vccio4 4 - - vccio4 4 - - vccio4 4 - - t15 vccio4 4 - - vccio4 4 - - vccio4 4 - - r8 vccio5 5 - - vccio5 5 - - vccio5 5 - - t10 vccio5 5 - - vccio5 5 - - vccio5 5 - - t11 vccio5 5 - - vccio5 5 - - vccio5 5 - - t8 vccio5 5 - - vccio5 5 - - vccio5 5 - - t9 vccio5 5 - - vccio5 5 - - vccio5 5 - - m7 vccio6 6 - - vccio6 6 - - vccio6 6 - - n7 vccio6 6 - - vccio6 6 - - vccio6 6 - - p7 vccio6 6 - - vccio6 6 - - vccio6 6 - - r7 vccio6 6 - - vccio6 6 - - vccio6 6 - - h7 vccio7 7 - - vccio7 7 - - vccio7 7 - - j7 vccio7 7 - - vccio7 7 - - vccio7 7 - - k7 vccio7 7 - - vccio7 7 - - vccio7 7 - - l7 vccio7 7 - - vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp10, lfxp15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 lfxp15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-43 pinout information lattice semiconductor latticexp family data sheet lfxp15 & lfxp20 logic signal connections: 484 fpbga ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function f5 programn 7 - - programn 7 - - e3 cclk 7 - - cclk 7 - - c1 pl2b 7 - - pl2b 7 - - - gndio7 7 - - gndio7 7 - - g5 pl3a 7 t 3 - pl3a 7 t 3 - g6 pl3b 7 c 3 - pl3b 7 c 3 - f4 pl4a 7 t - pl4a 7 t - f3 pl4b 7 c - pl4b 7 c - g4 pl5a 7 t 3 - pl5a 7 t 3 - g3 pl5b 7 c 3 - pl5b 7 c 3 - d1 pl6a 7 t 3 - pl6a 7 t 3 - d2 pl6b 7 c 3 - pl6b 7 c 3 - - gndio7 7 - - gndio7 7 - - e1 pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a e2 pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a h5 pl8a 7 t 3 - pl8a 7 t 3 - h6 pl8b 7 c 3 - pl8b 7 c 3 - h4 pl9a 7 - - pl9a 7 - - h3 pl10b 7 - vref1_7 pl10b 7 - vref1_7 f1 pl11a 7 t 3 dqs pl11a 7 t 3 dqs f2 pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - j5 pl12a 7 t - pl12a 7 t - j6 pl12b 7 c - pl12b 7 c - g1 pl13a 7 t 3 - pl13a 7 t 3 - g2 pl13b 7 c 3 - pl13b 7 c 3 - j4 pl15a 7 t 3 - pl15a 7 t 3 - j3 pl15b 7 c 3 - pl15b 7 c 3 - - gndio7 7 - - gndio7 7 - - h1 pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a h2 pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a j1 pl17a 7 t 3 - pl17a 7 t 3 - j2 pl17b 7 c 3 - pl17b 7 c 3 - k3 pl18a 7 - vref2_7 pl18a 7 - vref2_7 k2 pl19b 7 - - pl19b 7 - - k4 pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - k5 pl20b 7 c 3 - pl20b 7 c 3 - k1 pl21a 7 t - pl21a 7 t - l2 pl21b 7 c - pl21b 7 c - l4 pl22a 7 t 3 - pl22a 7 t 3 - l3 pl22b 7 c 3 - pl22b 7 c 3 -
4-44 pinout information lattice semiconductor latticexp family data sheet l1 - - - - pl23a 7 t 3 - m1 - - - - pl23b 7 c 3 - m2 - - - - pl24a 7 - - l5 vccp0 - - - vccp0 - - - n2 gndp0 - - - gndp0 - - - n1 - - - - pl25b 6 - - p2 - - - - pl26a 6 t 3 - p1 - - - - pl26b 6 c 3 - m4 pl23a 6 t 3 - pl27a 6 t 3 - m3 pl23b 6 c 3 - pl27b 6 c 3 - r2 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - r1 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 n3 pl25a 6 t 3 - pl29a 6 t 3 - n4 pl25b 6 c 3 - pl29b 6 c 3 - m5 pl26a 6 - - pl30a 6 - - n5 pl27b 6 - vref1_6 pl31b 6 - vref1_6 t2 pl28a 6 t 3 dqs pl32a 6 t 3 dqs t1 pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - u2 pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a u1 pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a p3 pl30a 6 t 3 - pl34a 6 t 3 - p4 pl30b 6 c 3 - pl34b 6 c 3 - p6 pl32a 6 t 3 - pl36a 6 t 3 - p5 pl32b 6 c 3 - pl36b 6 c 3 - - gndio6 6 - - gndio6 6 - - v2 pl33a 6 t - pl37a 6 t - v1 pl33b 6 c - pl37b 6 c - w2 pl34a 6 t 3 - pl38a 6 t 3 - w1 pl34b 6 c 3 - pl38b 6 c 3 - r3 pl35a 6 - vref2_6 pl39a 6 - vref2_6 r4 pl36b 6 - - pl40b 6 - - r6 pl37a 6 t 3 dqs pl41a 6 t 3 dqs r5 pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - y2 pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a y1 pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a t3 pl39a 6 t 3 - pl43a 6 t 3 - t4 pl39b 6 c 3 - pl43b 6 c 3 - w3 pl40a 6 t 3 - pl44a 6 t 3 - v3 pl40b 6 c 3 - pl44b 6 c 3 - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-45 pinout information lattice semiconductor latticexp family data sheet t6 pl41a 6 t - pl45a 6 t - t5 pl41b 6 c - pl45b 6 c - - gndio6 6 - - gndio6 6 - - u3 pl42a 6 t 3 - pl46a 6 t 3 - u4 pl42b 6 c 3 - pl46b 6 c 3 - v4 pl43a 6 - - pl47a 6 - - w4 sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - w5 initn 5 - - initn 5 - - y3 - - - - pb3b 5 - - - gndio5 5 - - gndio5 5 - - u5 - - - - pb4a 5 t - v5 - - - - pb4b 5 c - y4 - - - - pb5a 5 t - y5 - - - - pb5b 5 c - v6 - - - - pb6a 5 t - - gndio5 5 - - gndio5 5 - - u6 - - - - pb6b 5 c - w6 pb3a 5 t - pb7a 5 t - y6 pb3b 5 c - pb7b 5 c - aa2 pb4a 5 t - pb8a 5 t - aa3 pb4b 5 c - pb8b 5 c - v7 pb5a 5 - - pb9a 5 - - u7 pb6b 5 - - pb10b 5 - - y7 pb7a 5 t dqs pb11a 5 t dqs w7 pb7b 5 c - pb11b 5 c - aa4 pb8a 5 t - pb12a 5 t - - gndio5 5 - - gndio5 5 - - aa5 pb8b 5 c - pb12b 5 c - ab3 pb9a 5 t - pb13a 5 t - ab4 pb9b 5 c - pb13b 5 c - aa6 pb10a 5 t - pb14a 5 t - aa7 pb10b 5 c - pb14b 5 c - u8 pb11a 5 t - pb15a 5 t - v8 pb11b 5 c - pb15b 5 c - y8 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - w8 pb12b 5 c - pb16b 5 c - v9 pb13a 5 - - pb17a 5 - - u9 pb14b 5 - - pb18b 5 - - y9 pb15a 5 t dqs pb19a 5 t dqs w9 pb15b 5 c - pb19b 5 c - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-46 pinout information lattice semiconductor latticexp family data sheet ab5 pb16a 5 t - pb20a 5 t - ab6 pb16b 5 c - pb20b 5 c - aa8 pb17a 5 t - pb21a 5 t - aa9 pb17b 5 c vref2_5 pb21b 5 c vref2_5 w10 pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - v10 pb18b 5 c - pb22b 5 c - ab7 pb19a 5 t - pb23a 5 t - ab8 pb19b 5 c - pb23b 5 c - ab9 pb20a 5 t - pb24a 5 t - ab10 pb20b 5 c - pb24b 5 c - y10 pb21a 5 - - pb25a 5 - - aa10 pb22b 5 - - pb26b 5 - - w11 pb23a 5 t dqs pb27a 5 t dqs v11 pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - y11 pb24a 5 t - pb28a 5 t - aa11 pb24b 5 c - pb28b 5 c - ab11 pb25a 5 t - pb29a 5 t - ab12 pb25b 5 c - pb29b 5 c - y12 pb26a 4 t - pb30a 4 t - aa12 pb26b 4 c - pb30b 4 c - w12 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 v12 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - ab13 pb28a 4 t - pb32a 4 t - ab14 pb28b 4 c - pb32b 4 c - aa13 pb29a 4 - - pb33a 4 - - y13 pb30b 4 - - pb34b 4 - - ab15 pb31a 4 t dqs pb35a 4 t dqs ab16 pb31b 4 c vref1_4 pb35b 4 c vref1_4 v13 pb32a 4 t - pb36a 4 t - w13 pb32b 4 c - pb36b 4 c - aa14 pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - aa15 pb33b 4 c - pb37b 4 c - ab17 pb34a 4 t - pb38a 4 t - ab18 pb34b 4 c - pb38b 4 c - w14 pb35a 4 t - pb39a 4 t - y14 pb35b 4 c - pb39b 4 c - u14 pb36a 4 t vref2_4 pb40a 4 t vref2_4 v14 pb36b 4 c - pb40b 4 c - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-47 pinout information lattice semiconductor latticexp family data sheet ab19 pb37a 4 - - pb41a 4 - - ab20 pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - v15 pb39a 4 t dqs pb43a 4 t dqs u15 pb39b 4 c - pb43b 4 c - y15 pb40a 4 t - pb44a 4 t - w15 pb40b 4 c - pb44b 4 c - aa16 pb41a 4 t - pb45a 4 t - aa17 pb41b 4 c - pb45b 4 c - aa18 pb42a 4 t - pb46a 4 t - aa19 pb42b 4 c - pb46b 4 c - y16 pb43a 4 t - pb47a 4 t - w16 pb43b 4 c - pb47b 4 c - - gndio4 4 - - gndio4 4 - - aa20 pb44a 4 t - pb48a 4 t - aa21 pb44b 4 c - pb48b 4 c - y17 pb45a 4 - - pb49a 4 - - y18 pb46b 4 - - pb50b 4 - - y19 pb47a 4 t dqs pb51a 4 t dqs y20 pb47b 4 c - pb51b 4 c - v16 pb48a 4 t - pb52a 4 t - u16 pb48b 4 c - pb52b 4 c - - gndio4 4 - - gndio4 4 - - u18 - - - - pb53a 4 t - v18 - - - - pb53b 4 c - w19 - - - - pb54a 4 t - w18 - - - - pb54b 4 c - u17 - - - - pb55a 4 t - v17 - - - - pb55b 4 c - - gndio4 4 - - gndio4 4 - - w17 - - - - pb56a 4 - - - gndio3 3 - - gndio3 3 - - v19 pr43a 3 - - pr47a 3 - - u20 pr42b 3 c 3 - pr46b 3 c 3 - u19 pr42a 3 t 3 - pr46a 3 t 3 - v20 pr41b 3 c - pr45b 3 c - w20 pr41a 3 t - pr45a 3 t - t17 pr40b 3 c 3 - pr44b 3 c 3 - t18 pr40a 3 t 3 - pr44a 3 t 3 - t19 pr39b 3 c 3 - pr43b 3 c 3 - t20 pr39a 3 t 3 - pr43a 3 t 3 - - gndio3 3 - - gndio3 3 - - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-48 pinout information lattice semiconductor latticexp family data sheet r18 pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a r17 pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a y22 pr37b 3 c 3 - pr41b 3 c 3 - y21 pr37a 3 t 3 dqs pr41a 3 t 3 dqs w22 pr36b 3 - - pr40b 3 - - w21 pr35a 3 - vref1_3 pr39a 3 - vref1_3 p17 pr34b 3 c 3 - pr38b 3 c 3 - p18 pr34a 3 t 3 - pr38a 3 t 3 - - gndio3 3 - - gndio3 3 - - r19 pr33b 3 c - pr37b 3 c - r20 pr33a 3 t - pr37a 3 t - v22 pr32b 3 c 3 - pr36b 3 c 3 - v21 pr32a 3 t 3 - pr36a 3 t 3 - u22 pr30b 3 c 3 - pr34b 3 c 3 - u21 pr30a 3 t 3 - pr34a 3 t 3 - p19 pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a p20 pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - t22 pr28b 3 c 3 - pr32b 3 c 3 - t21 pr28a 3 t 3 dqs pr32a 3 t 3 dqs r22 pr27b 3 - - pr31b 3 - - r21 pr26a 3 - vref2_3 pr30a 3 - vref2_3 n19 pr25b 3 c 3 - pr29b 3 c 3 - n20 pr25a 3 t 3 - pr29a 3 t 3 - n18 pr24b 3 c - pr28b 3 c - m18 pr24a 3 t - pr28a 3 t - - gndio3 3 - - gndio3 3 - - p22 pr23b 3 c 3 - pr27b 3 c 3 - p21 pr23a 3 t 3 - pr27a 3 t 3 - n22 - - - - pr26b 3 c 3 - n21 - - - - pr26a 3 t 3 - m19 - - - - pr25b 3 - - m20 gndp1 - - - gndp1 - - - l18 vccp1 - - - vccp1 - - - m21 - - - - pr24a 2 - - m22 pr22b 2 c 3 - pr23b 2 c 3 - l22 pr22a 2 t 3 - pr23a 2 t 3 - - gndio2 2 - - gndio2 2 - - l19 - - - - pr22b 2 c 3 - l20 - - - - pr22a 2 t 3 - l21 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 k22 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-49 pinout information lattice semiconductor latticexp family data sheet j21 pr20b 2 c 3 - pr20b 2 c 3 - j22 pr20a 2 t 3 dqs pr20a 2 t 3 dqs k18 pr19b 2 - - pr19b 2 - - k19 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - k21 pr17b 2 c 3 - pr17b 2 c 3 - k20 pr17a 2 t 3 - pr17a 2 t 3 - h21 pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a h22 pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a j20 pr15b 2 c 3 - pr15b 2 c 3 - j19 pr15a 2 t 3 - pr15a 2 t 3 - - gndio2 2 - - gndio2 2 - - j17 pr13b 2 c 3 - pr13b 2 c 3 - j18 pr13a 2 t 3 - pr13a 2 t 3 - g21 pr12b 2 c - pr12b 2 c - g22 pr12a 2 t - pr12a 2 t - f21 pr11b 2 c 3 - pr11b 2 c 3 - f22 pr11a 2 t 3 dqs pr11a 2 t 3 dqs - gndio2 2 - - gndio2 2 - - h20 pr10b 2 - - pr10b 2 - - h19 pr9a 2 - vref2_2 pr9a 2 - vref2_2 h17 pr8b 2 c 3 - pr8b 2 c 3 - h18 pr8a 2 t 3 - pr8a 2 t 3 - e21 pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a e22 pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a d21 pr6b 2 c 3 - pr6b 2 c 3 - d22 pr6a 2 t 3 - pr6a 2 t 3 - g20 pr5b 2 c 3 - pr5b 2 c 3 - g19 pr5a 2 t 3 - pr5a 2 t 3 - g17 pr4b 2 c - pr4b 2 c - g18 pr4a 2 t - pr4a 2 t - - gndio2 2 - - gndio2 2 - - f18 pr3b 2 c 3 - pr3b 2 c 3 - f19 pr3a 2 t 3 - pr3a 2 t 3 - c22 pr2b 2 - - pr2b 2 - - f20 tdo - - - tdo - - - e20 vccj - - - vccj - - - d19 tdi - - - tdi - - - e19 tms - - - tms - - - d20 tck - - - tck - - - c20 - - - - pt56a 1 - - - gndio1 1 - - gndio1 1 - - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-50 pinout information lattice semiconductor latticexp family data sheet d18 - - - - pt55b 1 c - e18 - - - - pt55a 1 t - c19 - - - - pt54b 1 c - c18 - - - - pt54a 1 t - c21 - - - - pt53b 1 c - - gndio1 1 - - gndio1 1 - - b21 - - - - pt53a 1 t - e17 pt48b 1 c - pt52b 1 c - e16 pt48a 1 t - pt52a 1 t - c17 pt47b 1 c - pt51b 1 c - d17 pt47a 1 t dqs pt51a 1 t dqs f17 pt46b 1 - - pt50b 1 - - f16 pt45a 1 - - pt49a 1 - - c16 pt44b 1 c - pt48b 1 c - d16 pt44a 1 t - pt48a 1 t - a20 pt43b 1 c - pt47b 1 c - - gndio1 1 - - gndio1 1 - - b20 pt43a 1 t - pt47a 1 t - a19 pt42b 1 c - pt46b 1 c - b19 pt42a 1 t - pt46a 1 t - c15 pt41b 1 c - pt45b 1 c - d15 pt41a 1 t - pt45a 1 t - a18 pt40b 1 c - pt44b 1 c - b18 pt40a 1 t - pt44a 1 t - f15 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - e15 pt39a 1 t dqs pt43a 1 t dqs a17 pt38b 1 - - pt42b 1 - - b17 pt37a 1 - - pt41a 1 - - e14 pt36b 1 c - pt40b 1 c - f14 pt36a 1 t - pt40a 1 t - d14 pt35b 1 c - pt39b 1 c - c14 pt35a 1 t d0 pt39a 1 t d0 a16 pt34b 1 c d1 pt38b 1 c d1 b16 pt34a 1 t vref2_1 pt38a 1 t vref2_1 a15 pt33b 1 c - pt37b 1 c - b15 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - e13 pt32b 1 c d3 pt36b 1 c d3 d13 pt32a 1 t - pt36a 1 t - c13 pt31b 1 c - pt35b 1 c - b13 pt31a 1 t dqs pt35a 1 t dqs lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-51 pinout information lattice semiconductor latticexp family data sheet a14 pt30b 1 - - pt34b 1 - - b14 pt29a 1 - d4 pt33a 1 - d4 c12 pt28b 1 c - pt32b 1 c - b12 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - d12 pt27b 1 c d6 pt31b 1 c d6 e12 pt27a 1 t - pt31a 1 t - a13 pt26b 1 c d7 pt30b 1 c d7 a12 pt26a 1 t - pt30a 1 t - a11 pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - a10 pt25a 0 t cs1n pt29a 0 t cs1n d11 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 e11 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b11 pt23b 0 c - pt27b 0 c - c11 pt23a 0 t dqs pt27a 0 t dqs b9 pt22b 0 - - pt26b 0 - - a9 pt21a 0 - dout pt25a 0 - dout b8 pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - a8 pt20a 0 t writen pt24a 0 t writen e10 pt19b 0 c - pt23b 0 c - d10 pt19a 0 t vref1_0 pt23a 0 t vref1_0 c10 pt18b 0 c - pt22b 0 c - b10 pt18a 0 t di pt22a 0 t di b7 pt17b 0 c - pt21b 0 c - a7 pt17a 0 t csn pt21a 0 t csn c9 pt16b 0 c - pt20b 0 c - d9 pt16a 0 t - pt20a 0 t - b6 pt15b 0 c vref2_0 pt19b 0 c vref2_0 a6 pt15a 0 t dqs pt19a 0 t dqs f9 pt14b 0 - - pt18b 0 - - e9 pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - b5 pt12b 0 c - pt16b 0 c - a5 pt12a 0 t - pt16a 0 t - c8 pt11b 0 c - pt15b 0 c - d8 pt11a 0 t - pt15a 0 t - b4 pt10b 0 c - pt14b 0 c - a4 pt10a 0 t - pt14a 0 t - f8 pt9b 0 c - pt13b 0 c - e8 pt9a 0 t - pt13a 0 t - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-52 pinout information lattice semiconductor latticexp family data sheet b3 pt8b 0 c - pt12b 0 c - a3 pt8a 0 t - pt12a 0 t - - gndio0 0 - - gndio0 0 - - d7 pt7b 0 c - pt11b 0 c - c7 pt7a 0 t dqs pt11a 0 t dqs b2 pt6b 0 - - pt10b 0 - - c2 pt5a 0 - - pt9a 0 - - c3 pt4b 0 c - pt8b 0 c - d3 pt4a 0 t - pt8a 0 t - f7 pt3b 0 c - pt7b 0 c - e7 pt3a 0 t - pt7a 0 t - - gndio0 0 - - gndio0 0 - - c6 - - - - pt6b 0 c - d6 - - - - pt6a 0 t - c5 - - - - pt5b 0 c - c4 - - - - pt5a 0 t - f6 - - - - pt4b 0 c - e6 - - - - pt4a 0 t - - gndio0 0 - - gndio0 0 - - e4 - - - - pt3b 0 - - e5 cfg0 0 - - cfg0 0 - - d4 cfg1 0 - - cfg1 0 - - d5 done 0 - - done 0 - - a1 gnd - - - gnd - - - a2 gnd - - - gnd - - - a21 gnd - - - gnd - - - a22 gnd - - - gnd - - - aa1 gnd - - - gnd - - - aa22 gnd - - - gnd - - - ab1 gnd - - - gnd - - - ab2 gnd - - - gnd - - - ab21 gnd - - - gnd - - - ab22 gnd - - - gnd - - - b1 gnd - - - gnd - - - b22 gnd - - - gnd - - - h14 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j11 gnd - - - gnd - - - j12 gnd - - - gnd - - - j13 gnd - - - gnd - - - j14 gnd - - - gnd - - - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-53 pinout information lattice semiconductor latticexp family data sheet j15 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - k10 gnd - - - gnd - - - k11 gnd - - - gnd - - - k12 gnd - - - gnd - - - k13 gnd - - - gnd - - - k14 gnd - - - gnd - - - k9 gnd - - - gnd - - - l10 gnd - - - gnd - - - l11 gnd - - - gnd - - - l12 gnd - - - gnd - - - l13 gnd - - - gnd - - - l14 gnd - - - gnd - - - l9 gnd - - - gnd - - - m10 gnd - - - gnd - - - m11 gnd - - - gnd - - - m12 gnd - - - gnd - - - m13 gnd - - - gnd - - - m14 gnd - - - gnd - - - m9 gnd - - - gnd - - - n10 gnd - - - gnd - - - n11 gnd - - - gnd - - - n12 gnd - - - gnd - - - n13 gnd - - - gnd - - - n14 gnd - - - gnd - - - n9 gnd - - - gnd - - - p10 gnd - - - gnd - - - p11 gnd - - - gnd - - - p12 gnd - - - gnd - - - p13 gnd - - - gnd - - - p14 gnd - - - gnd - - - p15 gnd - - - gnd - - - p8 gnd - - - gnd - - - p9 gnd - - - gnd - - - r14 gnd - - - gnd - - - r9 gnd - - - gnd - - - f10 vcc - - - vcc - - - f13 vcc - - - vcc - - - g10 vcc - - - vcc - - - g13 vcc - - - vcc - - - g14 vcc - - - vcc - - - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-54 pinout information lattice semiconductor latticexp family data sheet g9 vcc - - - vcc - - - h15 vcc - - - vcc - - - h8 vcc - - - vcc - - - j16 vcc - - - vcc - - - j7 vcc - - - vcc - - - k16 vcc - - - vcc - - - k17 vcc - - - vcc - - - k6 vcc - - - vcc - - - k7 vcc - - - vcc - - - n16 vcc - - - vcc - - - n17 vcc - - - vcc - - - n6 vcc - - - vcc - - - n7 vcc - - - vcc - - - p16 vcc - - - vcc - - - p7 vcc - - - vcc - - - r15 vcc - - - vcc - - - r8 vcc - - - vcc - - - t10 vcc - - - vcc - - - t13 vcc - - - vcc - - - t14 vcc - - - vcc - - - t9 vcc - - - vcc - - - u10 vcc - - - vcc - - - u13 vcc - - - vcc - - - g15 vccaux - - - vccaux - - - g16 vccaux - - - vccaux - - - g7 vccaux - - - vccaux - - - g8 vccaux - - - vccaux - - - h16 vccaux - - - vccaux - - - h7 vccaux - - - vccaux - - - r16 vccaux - - - vccaux - - - r7 vccaux - - - vccaux - - - t15 vccaux - - - vccaux - - - t16 vccaux - - - vccaux - - - t7 vccaux - - - vccaux - - - t8 vccaux - - - vccaux - - - f11 vccio0 0 - - vccio0 0 - - g11 vccio0 0 - - vccio0 0 - - h10 vccio0 0 - - vccio0 0 - - h11 vccio0 0 - - vccio0 0 - - f12 vccio1 1 - - vccio1 1 - - g12 vccio1 1 - - vccio1 1 - - h12 vccio1 1 - - vccio1 1 - - lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-55 pinout information lattice semiconductor latticexp family data sheet h13 vccio1 1 - - vccio1 1 - - k15 vccio2 2 - - vccio2 2 - - l15 vccio2 2 - - vccio2 2 - - l16 vccio2 2 - - vccio2 2 - - l17 vccio2 2 - - vccio2 2 - - m15 vccio3 3 - - vccio3 3 - - m16 vccio3 3 - - vccio3 3 - - m17 vccio3 3 - - vccio3 3 - - n15 vccio3 3 - - vccio3 3 - - r12 vccio4 4 - - vccio4 4 - - r13 vccio4 4 - - vccio4 4 - - t12 vccio4 4 - - vccio4 4 - - u12 vccio4 4 - - vccio4 4 - - r10 vccio5 5 - - vccio5 5 - - r11 vccio5 5 - - vccio5 5 - - t11 vccio5 5 - - vccio5 5 - - u11 vccio5 5 - - vccio5 5 - - m6 vccio6 6 - - vccio6 6 - - m7 vccio6 6 - - vccio6 6 - - m8 vccio6 6 - - vccio6 6 - - n8 vccio6 6 - - vccio6 6 - - k8 vccio7 7 - - vccio7 7 - - l6 vccio7 7 - - vccio7 7 - - l7 vccio7 7 - - vccio7 7 - - l8 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number lfxp15 lfxp20 ball function bank differential dual function ball function bank differential dual function
december 2005 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 5-1 ds1001 ordering information_03.0 part number description ordering information (contact factory for speci? device availability) note: latticexp devices are dual marked. for example, the commercial speed grade lfxp10e-4f256c is also marked with industrial grade -3i (lfxp10e-3f256i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade does not have industrial markings. the markings appear as follows: lfxp xx x ?x xxxxxx x grade c = commercial i = industrial logic capacity 3k luts = 3 6k luts = 6 10k luts = 10 15k luts = 15 20k luts = 20 note: parts dual marked per table below. supply voltage c = 1.8v/2.5v/3.3v e = 1.2v speed 3 = slowest 4 5 = fastest package t100 = 100-pin tqfp t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f388 = 388-ball fpbga f484 = 484-ball fpbga tn100 = 100-pin lead-free tqfp tn144 = 144-pin lead-free tqfp qn208 = 208-pin lead-free pqfp fn256 = 256-ball lead-free fpbga fn388 = 388-ball lead-free fpbga fn484 = 484-ball lead-free fpbga device family latticexp fpga lfxp10e- 4f256c-3i datecode latticexp family data sheet ordering information
5-2 ordering information lattice semiconductor latticexp family data sheet conventional packaging commercial part number i/os voltage grade package pins temp. luts lfxp3c-3q208c 136 1.8/2.5/3.3v -3 pqfp 208 com 3.1k lfxp3c-4q208c 136 1.8/2.5/3.3v -4 pqfp 208 com 3.1k lfxp3c-5q208c 136 1.8/2.5/3.3v -5 pqfp 208 com 3.1k lfxp3c-3t144c 100 1.8/2.5/3.3v -3 tqfp 144 com 3.1k lfxp3c-4t144c 100 1.8/2.5/3.3v -4 tqfp 144 com 3.1k lfxp3c-5t144c 100 1.8/2.5/3.3v -5 tqfp 144 com 3.1k lfxp3c-3t100c 62 1.8/2.5/3.3v -3 tqfp 100 com 3.1k lfxp3c-4t100c 62 1.8/2.5/3.3v -4 tqfp 100 com 3.1k lfxp3c-5t100c 62 1.8/2.5/3.3v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 5.8k lfxp6c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 5.8k lfxp6c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 5.8k lfxp6c-3q208c 142 1.8/2.5/3.3v -3 pqfp 208 com 5.8k lfxp6c-4q208c 142 1.8/2.5/3.3v -4 pqfp 208 com 5.8k lfxp6c-5q208c 142 1.8/2.5/3.3v -5 pqfp 208 com 5.8k lfxp6c-3t144c 100 1.8/2.5/3.3v -3 tqfp 144 com 5.8k lfxp6c-4t144c 100 1.8/2.5/3.3v -4 tqfp 144 com 5.8k lfxp6c-5t144c 100 1.8/2.5/3.3v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3f388c 244 1.8/2.5/3.3v -3 fpbga 388 com 9.7k lfxp10c-4f388c 244 1.8/2.5/3.3v -4 fpbga 388 com 9.7k lfxp10c-5f388c 244 1.8/2.5/3.3v -5 fpbga 388 com 9.7k lfxp10c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 9.7k lfxp10c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 9.7k lfxp10c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 9.7k
5-3 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts lfxp15c-3f484c 300 1.8/2.5/3.3v -3 fpbga 484 com 15.5k lfxp15c-4f484c 300 1.8/2.5/3.3v -4 fpbga 484 com 15.5k lfxp15c-5f484c 300 1.8/2.5/3.3v -5 fpbga 484 com 15.5k lfxp15c-3f388c 268 1.8/2.5/3.3v -3 fpbga 388 com 15.5k lfxp15c-4f388c 268 1.8/2.5/3.3v -4 fpbga 388 com 15.5k lfxp15c-5f388c 268 1.8/2.5/3.3v -5 fpbga 388 com 15.5k lfxp15c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 15.5k lfxp15c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 15.5k lfxp15c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3f484c 340 1.8/2.5/3.3v -3 fpbga 484 com 19.7k lfxp20c-4f484c 340 1.8/2.5/3.3v -4 fpbga 484 com 19.7k lfxp20c-5f484c 340 1.8/2.5/3.3v -5 fpbga 484 com 19.7k lfxp20c-3f388c 268 1.8/2.5/3.3v -3 fpbga 388 com 19.7k lfxp20c-4f388c 268 1.8/2.5/3.3v -4 fpbga 388 com 19.7k lfxp20c-5f388c 268 1.8/2.5/3.3v -5 fpbga 388 com 19.7k lfxp20c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 19.7k lfxp20c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 19.7k lfxp20c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3q208c 136 1.2v -3 pqfp 208 com 3.1k lfxp3e-4q208c 136 1.2v -4 pqfp 208 com 3.1k lfxp3e-5q208c 136 1.2v -5 pqfp 208 com 3.1k lfxp3e-3t144c 100 1.2v -3 tqfp 144 com 3.1k lfxp3e-4t144c 100 1.2v -4 tqfp 144 com 3.1k lfxp3e-5t144c 100 1.2v -5 tqfp 144 com 3.1k lfxp3e-3t100c 62 1.2v -3 tqfp 100 com 3.1k lfxp3e-4t100c 62 1.2v -4 tqfp 100 com 3.1k lfxp3e-5t100c 62 1.2v -5 tqfp 100 com 3.1k
5-4 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts lfxp6e-3f256c 188 1.2v -3 fpbga 256 com 5.8k lfxp6e-4f256c 188 1.2v -4 fpbga 256 com 5.8k lfxp6e-5f256c 188 1.2v -5 fpbga 256 com 5.8k lfxp6e-3q208c 142 1.2v -3 pqfp 208 com 5.8k lfxp6e-4q208c 142 1.2v -4 pqfp 208 com 5.8k lfxp6e-5q208c 142 1.2v -5 pqfp 208 com 5.8k lfxp6e-3t144c 100 1.2v -3 tqfp 144 com 5.8k lfxp6e-4t144c 100 1.2v -4 tqfp 144 com 5.8k lfxp6e-5t144c 100 1.2v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3f388c 244 1.2v -3 fpbga 388 com 9.7k lfxp10e-4f388c 244 1.2v -4 fpbga 388 com 9.7k lfxp10e-5f388c 244 1.2v -5 fpbga 388 com 9.7k lfxp10e-3f256c 188 1.2v -3 fpbga 256 com 9.7k lfxp10e-4f256c 188 1.2v -4 fpbga 256 com 9.7k lfxp10e-5f256c 188 1.2v -5 fpbga 256 com 9.7k part number i/os voltage grade package pins temp. luts lfxp15e-3f484c 300 1.2v -3 fpbga 484 com 15.5k lfxp15e-4f484c 300 1.2v -4 fpbga 484 com 15.5k lfxp15e-5f484c 300 1.2v -5 fpbga 484 com 15.5k lfxp15e-3f388c 268 1.2v -3 fpbga 388 com 15.5k lfxp15e-4f388c 268 1.2v -4 fpbga 388 com 15.5k lfxp15e-5f388c 268 1.2v -5 fpbga 388 com 15.5k lfxp15e-3f256c 188 1.2v -3 fpbga 256 com 15.5k lfxp15e-4f256c 188 1.2v -4 fpbga 256 com 15.5k lfxp15e-5f256c 188 1.2v -5 fpbga 256 com 15.5k
5-5 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) industrial part number i/os voltage grade package pins temp. luts lfxp20e-3f484c 340 1.2v -3 fpbga 484 com 19.7k lfxp20e-4f484c 340 1.2v -4 fpbga 484 com 19.7k lfxp20e-5f484c 340 1.2v -5 fpbga 484 com 19.7k lfxp20e-3f388c 268 1.2v -3 fpbga 388 com 19.7k lfxp20e-4f388c 268 1.2v -4 fpbga 388 com 19.7k lfxp20e-5f388c 268 1.2v -5 fpbga 388 com 19.7k lfxp20e-3f256c 188 1.2v -3 fpbga 256 com 19.7k lfxp20e-4f256c 188 1.2v -4 fpbga 256 com 19.7k lfxp20e-5f256c 188 1.2v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3c-3q208i 136 1.8/2.5/3.3v -3 pqfp 208 ind 3.1k lfxp3c-4q208i 136 1.8/2.5/3.3v -4 pqfp 208 ind 3.1k lfxp3c-3t144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 3.1k lfxp3c-4t144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 3.1k lfxp3c-3t100i 62 1.8/2.5/3.3v -3 tqfp 100 ind 3.1k lfxp3c-4t100i 62 1.8/2.5/3.3v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 5.8k lfxp6c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 5.8k lfxp6c-3q208i 142 1.8/2.5/3.3v -3 pqfp 208 ind 5.8k lfxp6c-4q208i 142 1.8/2.5/3.3v -4 pqfp 208 ind 5.8k lfxp6c-3t144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 5.8k lfxp6c-4t144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3f388i 244 1.8/2.5/3.3v -3 fpbga 388 ind 9.7k lfxp10c-4f388i 244 1.8/2.5/3.3v -4 fpbga 388 ind 9.7k lfxp10c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 9.7k lfxp10c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 9.7k
5-6 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp15c-3f484i 300 1.8/2.5/3.3v -3 fpbga 484 ind 15.5k lfxp15c-4f484i 300 1.8/2.5/3.3v -4 fpbga 484 ind 15.5k lfxp15c-3f388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 15.5k lfxp15c-4f388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 15.5k lfxp15c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 15.5k lfxp15c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3f484i 340 1.8/2.5/3.3v -3 fpbga 484 ind 19.7k lfxp20c-4f484i 340 1.8/2.5/3.3v -4 fpbga 484 ind 19.7k lfxp20c-3f388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 19.7k lfxp20c-4f388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 19.7k lfxp20c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 19.7k lfxp20c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3q208i 136 1.2v -3 pqfp 208 ind 3.1k lfxp3e-4q208i 136 1.2v -4 pqfp 208 ind 3.1k lfxp3e-3t144i 100 1.2v -3 tqfp 144 ind 3.1k lfxp3e-4t144i 100 1.2v -4 tqfp 144 ind 3.1k lfxp3e-3t100i 62 1.2v -3 tqfp 100 ind 3.1k lfxp3e-4t100i 62 1.2v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3f256i 188 1.2v -3 fpbga 256 ind 5.8k lfxp6e-4f256i 188 1.2v -4 fpbga 256 ind 5.8k lfxp6e-3q208i 142 1.2v -3 pqfp 208 ind 5.8k lfxp6e-4q208i 142 1.2v -4 pqfp 208 ind 5.8k lfxp6e-3t144i 100 1.2v -3 tqfp 144 ind 5.8k lfxp6e-4t144i 100 1.2v -4 tqfp 144 ind 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3f388i 244 1.2v -3 fpbga 388 ind 9.7k lfxp10e-4f388i 244 1.2v -4 fpbga 388 ind 9.7k lfxp10e-3f256i 188 1.2v -3 fpbga 256 ind 9.7k lfxp10e-4f256i 188 1.2v -4 fpbga 256 ind 9.7k
5-7 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp15e-3f484i 300 1.2v -3 fpbga 484 ind 15.5k lfxp15e-4f484i 300 1.2v -4 fpbga 484 ind 15.5k lfxp15e-3f388i 268 1.2v -3 fpbga 388 ind 15.5k lfxp15e-4f388i 268 1.2v -4 fpbga 388 ind 15.5k lfxp15e-3f256i 188 1.2v -3 fpbga 256 ind 15.5k lfxp15e-4f256i 188 1.2v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3f484i 340 1.2v -3 fpbga 484 ind 19.7k lfxp20e-4f484i 340 1.2v -4 fpbga 484 ind 19.7k lfxp20e-3f388i 268 1.2v -3 fpbga 388 ind 19.7k lfxp20e-4f388i 268 1.2v -4 fpbga 388 ind 19.7k lfxp20e-3f256i 188 1.2v -3 fpbga 256 ind 19.7k lfxp20e-4f256i 188 1.2v -4 fpbga 256 ind 19.7k
5-8 ordering information lattice semiconductor latticexp family data sheet lead-free packaging commercial part number i/os voltage grade package pins temp. luts lfxp3c-3qn208c 136 1.8/2.5/3.3v -3 pqfp 208 com 3.1k lfxp3c-4qn208c 136 1.8/2.5/3.3v -4 pqfp 208 com 3.1k lfxp3c-5qn208c 136 1.8/2.5/3.3v -5 pqfp 208 com 3.1k lfxp3c-3tn144c 100 1.8/2.5/3.3v -3 tqfp 144 com 3.1k lfxp3c-4tn144c 100 1.8/2.5/3.3v -4 tqfp 144 com 3.1k lfxp3c-5tn144c 100 1.8/2.5/3.3v -5 tqfp 144 com 3.1k lfxp3c-3tn100c 62 1.8/2.5/3.3v -3 tqfp 100 com 3.1k lfxp3c-4tn100c 62 1.8/2.5/3.3v -4 tqfp 100 com 3.1k lfxp3c-5tn100c 62 1.8/2.5/3.3v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 5.8k lfxp6c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 5.8k lfxp6c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 5.8k lfxp6c-3qn208c 142 1.8/2.5/3.3v -3 pqfp 208 com 5.8k lfxp6c-4qn208c 142 1.8/2.5/3.3v -4 pqfp 208 com 5.8k lfxp6c-5qn208c 142 1.8/2.5/3.3v -5 pqfp 208 com 5.8k lfxp6c-3tn144c 100 1.8/2.5/3.3v -3 tqfp 144 com 5.8k lfxp6c-4tn144c 100 1.8/2.5/3.3v -4 tqfp 144 com 5.8k lfxp6c-5tn144c 100 1.8/2.5/3.3v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3fn388c 244 1.8/2.5/3.3v -3 fpbga 388 com 9.7k lfxp10c-4fn388c 244 1.8/2.5/3.3v -4 fpbga 388 com 9.7k lfxp10c-5fn388c 244 1.8/2.5/3.3v -5 fpbga 388 com 9.7k lfxp10c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 9.7k lfxp10c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 9.7k lfxp10c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 9.7k part number i/os voltage grade package pins temp. luts lfxp15c-3fn484c 300 1.8/2.5/3.3v -3 fpbga 484 com 15.5k lfxp15c-4fn484c 300 1.8/2.5/3.3v -4 fpbga 484 com 15.5k lfxp15c-5fn484c 300 1.8/2.5/3.3v -5 fpbga 484 com 15.5k lfxp15c-3fn388c 268 1.8/2.5/3.3v -3 fpbga 388 com 15.5k lfxp15c-4fn388c 268 1.8/2.5/3.3v -4 fpbga 388 com 15.5k lfxp15c-5fn388c 268 1.8/2.5/3.3v -5 fpbga 388 com 15.5k lfxp15c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 15.5k lfxp15c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 15.5k lfxp15c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 15.5k
5-9 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts lfxp20c-3fn484c 340 1.8/2.5/3.3v -3 fpbga 484 com 19.7k lfxp20c-4fn484c 340 1.8/2.5/3.3v -4 fpbga 484 com 19.7k lfxp20c-5fn484c 340 1.8/2.5/3.3v -5 fpbga 484 com 19.7k lfxp20c-3fn388c 268 1.8/2.5/3.3v -3 fpbga 388 com 19.7k lfxp20c-4fn388c 268 1.8/2.5/3.3v -4 fpbga 388 com 19.7k lfxp20c-5fn388c 268 1.8/2.5/3.3v -5 fpbga 388 com 19.7k lfxp20c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 19.7k lfxp20c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 19.7k lfxp20c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3qn208c 136 1.2v -3 pqfp 208 com 3.1k lfxp3e-4qn208c 136 1.2v -4 pqfp 208 com 3.1k lfxp3e-5qn208c 136 1.2v -5 pqfp 208 com 3.1k lfxp3e-3tn144c 100 1.2v -3 tqfp 144 com 3.1k lfxp3e-4tn144c 100 1.2v -4 tqfp 144 com 3.1k lfxp3e-5tn144c 100 1.2v -5 tqfp 144 com 3.1k lfxp3e-3tn100c 62 1.2v -3 tqfp 100 com 3.1k lfxp3e-4tn100c 62 1.2v -4 tqfp 100 com 3.1k lfxp3e-5tn100c 62 1.2v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3fn256c 188 1.2v -3 fpbga 256 com 5.8k lfxp6e-4fn256c 188 1.2v -4 fpbga 256 com 5.8k lfxp6e-5fn256c 188 1.2v -5 fpbga 256 com 5.8k lfxp6e-3qn208c 142 1.2v -3 pqfp 208 com 5.8k lfxp6e-4qn208c 142 1.2v -4 pqfp 208 com 5.8k lfxp6e-5qn208c 142 1.2v -5 pqfp 208 com 5.8k lfxp6e-3tn144c 100 1.2v -3 tqfp 144 com 5.8k lfxp6e-4tn144c 100 1.2v -4 tqfp 144 com 5.8k lfxp6e-5tn144c 100 1.2v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3fn388c 244 1.2v -3 fpbga 388 com 9.7k lfxp10e-4fn388c 244 1.2v -4 fpbga 388 com 9.7k lfxp10e-5fn388c 244 1.2v -5 fpbga 388 com 9.7k lfxp10e-3fn256c 188 1.2v -3 fpbga 256 com 9.7k lfxp10e-4fn256c 188 1.2v -4 fpbga 256 com 9.7k lfxp10e-5fn256c 188 1.2v -5 fpbga 256 com 9.7k
5-10 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) industrial part number i/os voltage grade package pins temp. luts lfxp15e-3fn484c 300 1.2v -3 fpbga 484 com 15.5k lfxp15e-4fn484c 300 1.2v -4 fpbga 484 com 15.5k lfxp15e-5fn484c 300 1.2v -5 fpbga 484 com 15.5k lfxp15e-3fn388c 268 1.2v -3 fpbga 388 com 15.5k lfxp15e-4fn388c 268 1.2v -4 fpbga 388 com 15.5k lfxp15e-5fn388c 268 1.2v -5 fpbga 388 com 15.5k lfxp15e-3fn256c 188 1.2v -3 fpbga 256 com 15.5k lfxp15e-4fn256c 188 1.2v -4 fpbga 256 com 15.5k lfxp15e-5fn256c 188 1.2v -5 fpbga 256 com 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3fn484c 340 1.2v -3 fpbga 484 com 19.7k lfxp20e-4fn484c 340 1.2v -4 fpbga 484 com 19.7k lfxp20e-5fn484c 340 1.2v -5 fpbga 484 com 19.7k lfxp20e-3fn388c 268 1.2v -3 fpbga 388 com 19.7k lfxp20e-4fn388c 268 1.2v -4 fpbga 388 com 19.7k lfxp20e-5fn388c 268 1.2v -5 fpbga 388 com 19.7k lfxp20e-3fn256c 188 1.2v -3 fpbga 256 com 19.7k lfxp20e-4fn256c 188 1.2v -4 fpbga 256 com 19.7k lfxp20e-5fn256c 188 1.2v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3c-3qn208i 136 1.8/2.5/3.3v -3 pqfp 208 ind 3.1k lfxp3c-4qn208i 136 1.8/2.5/3.3v -4 pqfp 208 ind 3.1k lfxp3c-3tn144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 3.1k lfxp3c-4tn144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 3.1k lfxp3c-3tn100i 62 1.8/2.5/3.3v -3 tqfp 100 ind 3.1k lfxp3c-4tn100i 62 1.8/2.5/3.3v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 5.8k lfxp6c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 5.8k lfxp6c-3qn208i 142 1.8/2.5/3.3v -3 pqfp 208 ind 5.8k lfxp6c-4qn208i 142 1.8/2.5/3.3v -4 pqfp 208 ind 5.8k lfxp6c-3tn144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 5.8k lfxp6c-4tn144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 5.8k
5-11 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp10c-3fn388i 244 1.8/2.5/3.3v -3 fpbga 388 ind 9.7k lfxp10c-4fn388i 244 1.8/2.5/3.3v -4 fpbga 388 ind 9.7k lfxp10c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 9.7k lfxp10c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 9.7k part number i/os voltage grade package pins temp. luts lfxp15c-3fn484i 300 1.8/2.5/3.3v -3 fpbga 484 ind 15.5k lfxp15c-4fn484i 300 1.8/2.5/3.3v -4 fpbga 484 ind 15.5k lfxp15c-3fn388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 15.5k lfxp15c-4fn388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 15.5k lfxp15c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 15.5k lfxp15c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3fn484i 340 1.8/2.5/3.3v -3 fpbga 484 ind 19.7k lfxp20c-4fn484i 340 1.8/2.5/3.3v -4 fpbga 484 ind 19.7k lfxp20c-3fn388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 19.7k lfxp20c-4fn388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 19.7k lfxp20c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 19.7k lfxp20c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3qn208i 136 1.2v -3 pqfp 208 ind 3.1k lfxp3e-4qn208i 136 1.2v -4 pqfp 208 ind 3.1k lfxp3e-3tn144i 100 1.2v -3 tqfp 144 ind 3.1k lfxp3e-4tn144i 100 1.2v -4 tqfp 144 ind 3.1k lfxp3e-3tn100i 62 1.2v -3 tqfp 100 ind 3.1k lfxp3e-4tn100i 62 1.2v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3fn256i 188 1.2v -3 fpbga 256 ind 5.8k lfxp6e-4fn256i 188 1.2v -4 fpbga 256 ind 5.8k lfxp6e-3qn208i 142 1.2v -3 pqfp 208 ind 5.8k lfxp6e-4qn208i 142 1.2v -4 pqfp 208 ind 5.8k lfxp6e-3tn144i 100 1.2v -3 tqfp 144 ind 5.8k lfxp6e-4tn144i 100 1.2v -4 tqfp 144 ind 5.8k
5-12 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp10e-3fn388i 244 1.2v -3 fpbga 388 ind 9.7k lfxp10e-4fn388i 244 1.2v -4 fpbga 388 ind 9.7k lfxp10e-3fn256i 188 1.2v -3 fpbga 256 ind 9.7k lfxp10e-4fn256i 188 1.2v -4 fpbga 256 ind 9.7k part number i/os voltage grade package pins temp. luts lfxp15e-3fn484i 300 1.2v -3 fpbga 484 ind 15.5k lfxp15e-4fn484i 300 1.2v -4 fpbga 484 ind 15.5k lfxp15e-3fn388i 268 1.2v -3 fpbga 388 ind 15.5k lfxp15e-4fn388i 268 1.2v -4 fpbga 388 ind 15.5k lfxp15e-3fn256i 188 1.2v -3 fpbga 256 ind 15.5k lfxp15e-4fn256i 188 1.2v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3fn484i 340 1.2v -3 fpbga 484 ind 19.7k lfxp20e-4fn484i 340 1.2v -4 fpbga 484 ind 19.7k lfxp20e-3fn388i 268 1.2v -3 fpbga 388 ind 19.7k lfxp20e-4fn388i 268 1.2v -4 fpbga 388 ind 19.7k lfxp20e-3fn256i 188 1.2v -3 fpbga 256 ind 19.7k lfxp20e-4fn256i 188 1.2v -4 fpbga 256 ind 19.7k
december 2005 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1001 further information_01.2 for further information a variety of technical notes for the latticexp family are available on the lattice web site at www .latticesemi.com . ? latticeecp/ec and latticexp sysio usage guide (tn1056) ? lattice isptracy usage guide (tn1054) ? latticeecp/ec and latticexp sysclock pll design and usage guide (tn1049) ? memory usage guide for latticeecp/ec and latticexp devices (tn1051) ? latticeecp/ec and xp ddr usage guide (tn1050) ? estimating power using power calculator for latticeecp/ec and latticexp devices (tn1052) ? latticexp sysconfig usage guide (tn1082) for further information on interface standards refer to the following web sites: ? jedec standards (lvttl, lvcmos, sstl, hstl): www .jedec.org ?pci: www .pcisig.com latticexp family data sheet supplemental information
february 2007 data sheet ds1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 7-1 revision history date version section change summary february 2005 01.0 initial release. april 2005 01.1 architecture ebr memory support section updated with clari?ation. may 2005 01.2 introduction added transfr recon?uration to features section. architecture added transfr section. june 2005 01.3 pinout information added pinout information for lfxp3, lfxp6, lfxp15 and lfxp20. july 2005 02.0 introduction updated xp6, xp15 and xp20 ebr sram bits and block numbers. architecture updated per quadrant primary clock selection ?ure. added typical i/o behavior during power-up section. updated device con?uration section under con?uration and testing. dc and switching characteristics clari?d hot socketing speci?ation updated supply current (standby) table updated initialization supply current table added programming and erase flash supply current table added lvds emulation section. updated lvds25e output termination example ?ure and lvds25e dc conditions table. updated differential lvpecl diagram and lvpecl dc conditions table. deleted 5v tolerant input buffer section. updated rsds ?ure and rsds dc conditions table. updated sysconfig port timing speci?ations updated jtag port timing speci?ations. added flash download time table. pinout information updated signal descriptions table. updated logic signal connections dual function column. ordering information added lead-free ordering part numbers. july 2005 02.1 dc and switching characteristics clari?ation of flash programming junction temperature august 2005 02.2 introduction added sleep mode feature. architecture added sleep mode section. dc and switching characteristics added sleep mode supply current table added sleep mode timing section pinout information added sleepn and toe signal names, descriptions and footnotes. added sleepn and toe to pinout information and footnotes. added footnote 3 to logic signal connections tables for clari?ation on emulated lvds output. september 2005 03.0 architecture added clari?ation of pci clamp. added clari?ation to sleepn pin characteristics section. dc and switching characteristics dc characteristics, added footnote 4 for clari?ation. updated supply current (sleep mode), supply current (standby), initialization supply current, and programming and erase flash supply current typical numbers. latticexp family data sheet revision history
7-2 revision history lattice semiconductor latticexp family data sheet september 2005 (cont.) 03.0 (cont.) dc and switching characteristics (cont.) updated typical building block function performance timing numbers. updated external switching characteristics timing numbers. updated internal timing parameters. updated latticexp family timing adders. updated latticexp "c" sleep mode timing numbers. updated jtag port timing numbers. pinout information added clari?ation to sleepn and toe description. clari?ation of dedicated lvds outputs. supplemental information updated list of technical notes. september 2005 03.1 pinout information power supply and nc connections table corrected vccp1 pin number for 208 pqfp. december 2005 04.0 introduction moved data sheet from advance to final. architecture added clari?ation to typical i/o behavior during power-up section. dc and switching characteristics added clari?ation to recommended operating conditions. updated timing numbers. pinout information updated signal descriptions table. added clari?ation to differential i/o per bank. updated differential dedicated lvds output support. ordering information added 208 pqfp lead-free package and ordering part numbers. february 2006 04.1 pinout information corrected description of signal names vref1(x) and vref2(x). march 2006 04.2 dc and switching characteristics corrected condition for iil and iih. march 2006 04.3 dc and switching characteristics added clari?ation to recommended operating conditions for vccaux. april 2006 04.4 pinout information removed bank designator "5" from sleepn/toe ball function. may 2006 04.5 dc and switching characteristics added footnote 2 regarding threshold level for programn to syscon- fig port timing speci?ations table. june 2006 04.6 dc and switching characteristics corrected lvds25e output termination example. august 2006 04.7 architecture added clari?ation to typical i/o behavior during power-up section. added clari?ation to left and right sysio buffer pair section. dc and switching characteristics changes to lvds25e output termination example diagram. december 2006 04.8 architecture ebr asynchronous reset section added. february 2007 04.9 architecture updated ebr asynchronous reset section. date version section change summary
section ii. latticexp family technical notes
march 2006 technical note tn1056 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 8-1 tn1056 _03.3 introduction the latticeecp, latticeec and latticexp sysio buffers give the designer the ability to easily interface with other devices using advanced system i/o standards. this technical note describes the sysio standards avail- able and how they can be implemented using lattices design software. sysio buffer overview the latticeecp/ec and latticexp sysio interfaces contain multiple programmable i/o cells (pic) blocks. in the case of the latticeec and latticeecp devices, each pic contains two programmable i/os (pio), pioa and piob, connected to their respective sysio buffers. in the latticexp device, each pic also contains two pios, pioa and piob, but every fourth pic will have only pioa. two adjacent pios can be joined to provide a differential i/o pair (labeled as ? and ??. each programmable i/o (pio) includes a sysio buffer and i/o logic (iologic). the latticeecp/ec and lat- ticexp sysio buffers support a variety of single-ended and differential signaling standards. the sysio buffer also supports the dqs strobe signal that is required for interfacing with the ddr memory. one of every 16 pios in the latticeecp/ec and one of every 14 pios in the case of the latticexp contains a delay element to facilitate the generation of dqs signals. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. for more information on the architecture of the sysio buffer, please refer to the device data sheets. the iologic includes input, output and tristate registers that implement both single data rate (sdr) and double data rate (ddr) applications along with the necessary clock and data selection logic. programmable delay lines and dedicated logic within the iologic are used to provide the required shift to incoming clock and data signals and the delay required by dqs inputs in ddr memory. the ddr implementation in the iologic and the ddr memory interface support are discussed in more details in lattice technical note number tn1050, latticeecp/ec ddr usage guide. supported sysio standards the latticeecp/ec and latticexp sysio buffer supports both single-ended and differential standards. single- ended standards can be further subdivided into lvcmos, lvttl, pci and other standards. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has indi- vidually con?urable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). other single-ended standards supported include sstl and hstl. differential standards supported include lvds, rsds, blvds, lvpecl, differential sstl and differential hstl. table 8-1 lists the sysio standards sup- ported in the lattice ec/ecp and latticexp devices. latticeecp/ec and latticexp sysio usage guide
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-2 table 8-1. supported sysio standards sysio banking scheme latticeecp/ec and latticexp devices have eight programmable sysio banks, two per side. each sysio bank has a v ccio supply voltage and two reference voltages, v ref1 and v ref2. on the top and bottom banks, the sysio buffer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the left and right side sysio buffer pair along with the two single-ended output and input drivers will also have a differential driver. the referenced input buffer can also be con?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. figure 8-1 shows the eight banks and their associated supplies. v ccio v ref (v) standard min. typ. max. min. typ. max. lvcmos 3.3 3.135 3.3 3.465 lvcmos 2.5 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 1.14 1.2 1.26 lvttl 3.135 3.3 3.465 pci 3.135 3.3 3.465 sstl18 class i 1.71 2.5 1.89 0.833 0.9 0.969 sstl2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl15 class iii 1.425 1.5 1.575 0.9 hstl 18 class i, ii 1.71 1.8 1.89 0.9 hstl 18 class iii 1.71 1.8 1.89 1.08 lvds 2.375 2.5 2.625 lvpecl 1 3.135 3.3 3.465 blvds 1 2.375 2.5 2.625 rsds 1 2.375 2.5 2.625 1. inputs on chip. outputs are implemented with the addition of external resistors.
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-3 figure 8-1. sysio banking v ccio (1.2v/1.5v/1.8v/2.5v/3.3v) each bank has a separate v ccio supply that powers the single-ended output drivers and the ratioed input buffers such as lvttl, lvcmos, and pci. lvttl, lvcmos3.3, lvcmos2.5 and lvcmos1.2 also have ?ed threshold options allowing them to be placed in any bank. the vccio voltage applied to the bank determines the ratioed input standards that can be supported in that bank. it is also used to power the differential output drivers. v ccaux (3.3v) in addition to the bank v ccio supplies, devices have a v cc core logic power supply, and a v ccaux auxiliary supply that powers the differential and referenced input buffers. v ccaux is required because v cc does not have enough headroom to satisfy the common-mode range requirements of these drivers and input buffers. v ccj (1.2v/1.5v/1.8v/2.5v/3.3v) the jtag pins have a separate v ccj power supply that is independent of the bank v ccio supplies. v ccj deter- mines the electrical characteristics of the lvcmos jtag pins, both the output high level and the input threshold. input reference voltage (v ref1, v ref2 ) each bank can support up to two separate v ref input voltages, v ref1 and v ref2 , that are used to set the threshold for the referenced input buffers. the location of these v ref pins is pre-determined within the bank. these pins can be used as regular i/os if the bank does not require a v ref voltage. v ref1 for ddr memory interface when interfacing to ddr memory, the v ref1 input must be used as the reference voltage for the dqs and dq input from the memory. a voltage divider between v ref1 and gnd is used to generate an on-chip reference volt- v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd bank 6 v ccio6 v ref2(6) v ref1( 5) gnd bank 5 v ccio5 v ref2( 5) v ref1( 4) gnd bank 4 v ccio4 v ref2( 4) v ref1 ( 0) gnd bank 0 v ccio 0 v ref2 ( 0) v ref1 (1 ) gnd bank 1 v ccio 1 v ref2 (1)
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-4 age that is used by the dqs transition detector circuit. this voltage divider is only present on v ref1 it is not avail- able on v ref2. for more information on the dqs transition detect logic and its implementation please refer to lattice technical note number tn1050, latticeecp/ec ddr usage guide. mixed voltage support in a bank the latticeecp/ec and latticexp sysio buffer is connected to three parallel ratioed input buffers. these three par- allel buffers are connected to v ccio, v ccaux and to v cc giving support for thresholds that track with v ccio as well as ?ed thresholds for 3.3v (v ccaux ) and 1.2v (v cc ) inputs. this allows the input threshold for ratioed buffers to be assigned on a pin-by-pin basis, rather than tracking it with v ccio. this option is available for all 1.2v, 2.5v and 3.3v ratioed inputs and is independent of the bank v ccio voltage. for example, if the bank v ccio is 1.8v, it is possible to have 1.2v and 3.3v ratioed input buffers with ?ed thresholds, as well as 2.5v ratioed inputs with tracking thresh- olds. prior to device con?uration, the ratioed input thresholds always track the bank v ccio, this option only takes effect after con?uration. output standards within a bank are always set by v ccio. table 8-2 shows the sysio standards that the user can mix in the same bank. table 8-2. mixed voltage support v ccio input sysio standards output sysio standards 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v yes yes yes yes 1.5v yes yes yes yes yes 1.8v yes yes yes yes yes 2.5v yes yes yes yes 3.3v yes yes yes yes
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-5 sysio standards supported in each bank table 8-3. i/o standards supported by various banks lvcmos buffer con?urations all lvcmos buffers have programmable pull, programmable drive and programmable slew con?urations that can be set in the software. programmable pull-up/pull-down/buskeeper when con?ured as lvcmos or lvttl, each sysio buffer has a weak pull-up, a weak pull-down resistor and a weak buskeeper (bus hold latch) available. each i/o can independently be con?ured to have one of these features or none of them. programmable drive each lvcmos or lvttl output buffer pin has a programmable drive strength option. this option can be set for each i/o independently. the drive strength setting available are 2ma, 4ma, 6ma, 8ma, 12ma, 16ma and 20ma. actual options available vary by the i/o voltage. the user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength. description top side banks 0-1 right side banks 2-3 bottom side banks 4-5 left side banks 6-7 types of i/o buffers single-ended single-ended and differ- ential single-ended single-ended and differ- ential output standards supported lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl25 class i, ii sstl33 class i, ii hstl15 class i, iii hstl18_i, ii, iii sstl18d class i, sstl25d class i, ii sstl33d class i, ii hstl15d class i, iii, hstl18d class i, iii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl25 class i, ii sstl33 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii sstl33d class i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii, sstl33d class i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii, sstl33d_i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential clock inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential pci support pci33 with clamp pci33 no clamp pci33 with clamp pci no clamp lvds output buffers lvds (3.5ma) buffers lvds (3.5ma) buffers 1. these differential standards are implemented by using complementary lvcmos driver with external resistor pack.
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-6 the programmable drive feature also allows the user to match to the impedance of the transmission line. table 8-4 shows the drive current setting required to match 50 transmission line with 50 and 200 terminations. table 8-4. impedance matching using programmable drive strength the actual impedance matching may vary on the transmission line design and the load. to ?d the best matching, it is recommended to drive the transmission line with different combinations of i/o standards and drive strengths that best match the line impedance. lattice provides ibis buffer models for the users to further analyze the imped- ance matching. the ?ure below shows how this impedance matching is done for a 50 transmission line with 200 termination using lvcmos18 i/o buffers programmed to drive 16ma, 12ma, 8ma and 4ma. from this experiment it is empiri- cal that the best matching is achieved with the 8ma drive setting. figure 8-2. impedance matching for a 50 transmission line with 200 termination 50 transmission line termination ( ) i/o standard drive strength (ma) 200 lvcmos18 8 lvcmos33 12 50 lvcmos18 16 lvcmos33 20 lvcmos18 16ma lvcmos18 12ma
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-7 figure 7-2. impedance matching for a 50 transmission line with 200 termination (cont.) programmable slew rate each lvcmos or lvttl output buffer pin also has a programmable output slew rate control that can be con?ured for either low noise or high-speed performance. each i/o pin has an individual slew rate control. this allows slew rate control to be speci?d on pin-by-pin basis. this slew rate control affects both the rising edges and the falling edges. open drain control all lvcmos and lvttl output buffers can be con?ured to function as open drain outputs. the user can imple- ment an open drain output by turning on the opendrain attribute in the software. the software implements open drain in the latticeecp/ec and latticexp devices by connecting the data and tristate input of the output buffer. software will implement open drain using this method for simple output buffers. if the user wants to assign open drain functionality to a bidirectional i/o, a similar implementation is required in the hdl design. this can be accomplished by combining the equations for the output enable with the output data. the function of an open drain output is to drive a high z when the data to the output buffer is driven high and drive a low when the data to the output buffer is driven low. differential sstl and hstl support the single-ended driver associated with the complementary ? pad can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. this allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. this is used for driv- ing complementary sstl and hstl signals (as required by the differential sstl and hstl clock inputs on syn- chronous dram and synchronous sram devices respectively). this capability is also used in conjunction with off- chip resistors to emulate lvpecl and blvds output drivers. pci support with programmable pciclamp each sysio buffer can be con?ured to support pci33. the buffers on the top and bottom of the device have an optional pci clamp diode that may optionally be speci?d in the isplever design tool. the programmable pciclamp can be turned on or off. this option is available on each i/o independently on the top and bottom banks. lvcmos18 8ma lvcmos18 4ma
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-8 5v interface with pci clamp diode all the i/os on the top and bottom sides of the device (banks 0, 1, 4, and 5) have a clamp diode that is used to clamp the voltage at the input to v ccio . this is especially used for pci i/o standards. this clamp diode can be used along with an external resistor to make an input 5v tolerant. figure 8-3. 5v tolerant input buffer the value of this external resistor will depend on the pci clamp diode characteristics. you can ?d the voltage vs. current data across this diode in the device ibis model. in order to interface to 5v input, it is recommended to set the v ccio between 2.5v to 3.3v. below is an example for calculating the value of this external resistor when v ccio is 2.75v. maximum voltage at input pin, v inmax = 3.75v (see device data sheet for more details) bank v ccio = 2.75v maximum voltage drop across clamp diode, v d = v inmax - v ccio = 3.75 - 2.75 =1v the current across the clamp diode at v d can be found in the power clamp data of the ibis ?e. below is the power clamp portion of the ibis ?e for a lvcmos3.3 input model with pci clamp turned on. when v d is 1v, the clamp diode current is i d = 27.4ma. table 8-5. power clamp data from ibis model assume the maximum output voltage of the driving device is v ext = 5.25v. the value of the external resistor can then be calculated as follows: voltage i (max.) units -1.40 72.5 ma -1.30 61.2 ma -1.20 49.9 ma -1.10 38.6 ma -1.00 27.4 ma -0.90 16.9 ma -0.80 9.52 ma -0.70 5.35 ma -0.60 2.31 ma -0.50 550.8 ? -0.40 58.0 ? -0.30 3.61 ? -0.20 0.07917 ? -0.10 0.0009129 ? 0.00 0.0001432 ? external resistor pci clamp diode 5v input v ccio
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-9 r ext = (v ext - v inmax )/i d = (5.25v - 3.75v)/27.4 = 54.8 ohm if the v ccio of the bank is increased, it will also increase the value of the external resistor required. changing the bank v ccio will also change the value of the input threshold voltage. programmable input delay each input can optionally be delayed before it is passed to the core logic or input registers. the primary use for the input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. to arrive at zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. this option can be turned on or off for each i/o independently in the software using the fixeddelay attribute. this attribute is described in more detail in the software sysio attributes section. appendix a shows how this feature can be enabled in the software using hdl attributes. software sysio attributes sysio attributes can be speci?d in the hdl, using the preference editor gui or in the ascii preference ?e (.prf) ?e directly. appendices a, b and c list examples of how these can be assigned using each of the methods men- tioned above. this section describes in detail each of these attributes. io_type this is used to set the sysio standard for an i/o. the v ccio required to set these i/o standards are embedded in the attribute names itself. there is no separate attribute to set the v ccio requirements. table 8-6 lists the available i/o types.
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-10 table 8-6. i/o_type attribute values opendrain lvcmos and lvttl i/o standards can be set to open drain con?uration by using the opendrain attribute. values: on, off default: off drive the drive strength attribute is available for lvttl and lvcmos output standards. these can be set or each i/o pin individually. sysio signaling standard io_type default (for latticeecp/ec) lvcmos12 default (for latticexp) lvcmos25 lvds 2.5v lvds25 rsds rsds emulated lvds 2.5v lvds25e 1 bus lvds 2.5v blvds25 1 lvpecl 3.3v lvpecl33 1 hstl18 class i, ii and iii hstl18_i, hstl18_ii, hstl18_iii differential hstl 18 class i, ii and iii hstl18d_i hstl18d_ii hstl18d_iii hstl 15 class i and iii hstl15_i hstl15_iii differential hstl 15 class i and iii hstl15d_i hstl15d_iii sstl 33 class i and ii sstl33_i, sstl33_ii differential sstl 33 class i and ii sstl33d_i sstl3d_ii sstl 25 class i and ii sstl25_i sstl25_ii differential sstl 25 class i and ii sstl25d_i sstl25d_ii sstl 18 class i sstl18_i differential sstl 18 class i sstl18d_i lvttl lvttl33 3.3v lvcmos lvcmos33 2.5v lvcmos lvcmos25 1.8v lvcmos lvcmos18 1.5v lvcmos lvcmos15 1.2v lvcmos lvcmos12 3.3v pci pci33 1. these differential standards are implemented by using complementary lvcmos driver with external resistor pack.
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-11 values: na, 2, 4, 8, 12, 16, 20 latticeecp/ec default: 6 latticexp default: 8 the programmable drive available on a pad will depend on the v ccio. table 8-7 shows the drive strength available for different v ccio. table 8-7. programmable drive strength values at various v ccio voltages pullmode the pullmode attribute is available for all the lvtll and lvcmos inputs and outputs. this attribute can be enabled for each i/o independently. values: up, down, none, keeper default: up pciclamp pci33 inputs and outputs on the top and bottom of the device have an optional pci clamp that is enabled via the pciclamp attribute. the pciclamp is also available for all lvcmos33 and lvttl inputs and outputs. values: on, off default: off slewrate the slewrate attribute is available for all lvttl and lvcmos output drivers. each i/o pin has an individual slew rate control. this allows the designer to specify the slew rate control on a pin-by-pin basis. values: fast, slow default: fast fixeddelay the fixeddelay attribute is available to each input pin. when enabled, this attribute is used to achieve zero hold time for the input registers when using global clock. values: true, false default: false din/dout this attribute can be used when i/o registers need to be assigned. using din will assert an input register and using the dout attribute will assert an output register in the design. by default the software will try to assign the i/o registers if applicable. the user can turn this off by using the synthesis attribute or using the preference editor of the software. these attributes can only be applied on registers. drive v ccio 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 2x 4 xxxx 6x 8 xxxx 12 xxx 16 xxx 20 x x
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-12 loc this attribute can be used to make pin assignments to the i/o ports in the design. this attribute is only used when the pin assignments are made in hdl source. pins assignments can be made directly using the gui in the prefer- ence editor of the software. the appendices explain this in more detail. design considerations and usage this section discusses some of design rules and considerations that need to be taken into account when designing with the latticeecp/ecp and latticexp sysio buffer. banking rules if v ccio or v ccj for any bank is set to 3.3v, it is recommended that it be connected to the same power sup- ply as v ccaux, thus minimizing leakage. if v ccio or v ccj for any bank is set to 1.2v, it is recommended that it be connected to the same power sup- ply as v cc, thus minimizing leakage. when implementing ddr memory interfaces, the v ref1 of the bank is used to provide reference to the interface pins and cannot be used to power any other referenced inputs. only the top and bottom banks (banks 0, 1, 4, and 5) will support pci clamps. the left and right side (banks 2, 3, 6 and 7) do not support pci clamp, but will support true lvds output. differential i/o rules all the banks can support lvds input buffers. only the banks on the right and left side (banks 2, 3, 6 and 7) will support true differential output buffers. the banks on the top and bottom will support the lvds input buffers but will not support true lvds outputs. the user can use emulated lvds output buffers on these banks. all banks support emulated differential buffers using external resistor pack and complementary lvcmos drivers. in latticexp devices, not all pios have lvds capability. only four out of every seven i/os can provide lvds buffer capability. in latticeecp/ec devices, there are no restrictions on the number of i/os that can support lvds. in both cases lvds can only be assigned to the true pad. refer to the device data sheets to see the pin listing for all the lvds pairs. assigning v ref / v ref groups for referenced inputs each bank has two dedicated v ref input pins, v ref1 and v ref2. buffers can be grouped to a particular v ref rail, v ref1 or v ref2. this grouping is done by assigning a pgroup vref preference along with the locate pgroup preference. preference syntax pgroup [(vref )+] (comp )+; locate pgroup bank ; locate vref site ; example of vref groups pgroup ?vref_pg1? vref ?ref1? comp ?ah(0)? comp ?ah(1)? comp ?ah(2)? comp ?ah(3)? comp ?ah(4)? comp ?ah(5)? comp ?ah(6)? comp ?ah(7)?; pgroup ?vref_pg2? vref ?ref2? comp ?al(0)? comp ?al(1)? comp ?al(2)? comp ?al(3)? comp ?al(4)? comp ?al(5)? comp ?al(6)? comp ?al(7)?; locate vref ?ref1? site pr29c; locate vref ?ref2? site pr48b;
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-13 or locate pgroup ? vref_pg1? bank 2; locate pgroup ? vref_pg2? bank 2; the second example show v ref groups, ?ref_pg1 assigned to v ref ?ef1 and ?ref_pg2 assigned to ?ef2? v ref must then be locked to either v ref1 or v ref2 using locate preference. or, the user can simply designate to which bank v ref group should be located. the software will then assign these to either v ref1 or v ref2 of the bank. if the pgroup vref is not used, the software will automatically group all pins that need the same v ref reference voltage. this preference is most useful when there is more than one bus using the same reference voltage and the user wants to associate each of these buses to different v ref resources. differential i/o implementation the latticeecp/ec and latticexp devices support a variety of differential standards as detailed in the following section. lvds true lvds (lvds25) drivers are available on the left and right side of the devices. lvds input support is provided on all sides of the device. all four sides support lvds using complementary lvcmos drivers with external resis- tors (lvds25e). please refer to the latticeecp/ec and latticexp data sheets for a more detailed explanation of these lvds imple- mentations. blvds all single-ended sysio buffer pairs in the latticeecp family support the bus-lvds standard using complementary lvcmos drivers with external resistors. please refer to the latticeecp/ec and latticexp data sheets to learn more about blvds implementation. rsds all single-ended sysio buffers pairs in the latticeecp family support the rsds standard using complementary lvcmos drivers with external resistors. this mode uses lvds25e with an alternative resistor pack. please refer to the latticeecp/ec and latticexp data sheets for a detailed explanation of rsds implementation. lvpecl all the sysio buffers will support lvpecl inputs. lvpecl outputs are supported using a complementary lvcmos driver with external resistors. please refer to the latticeecp/ec and latticexp data sheets for further information on lvpecl implementation. differential sstl and hstl all single-ended sysio buffers pairs in the latticeecp family support differential sstl and hstl. please refer to the latticeecp/ec and latticexp data sheets for a detailed explanation of differential hstl and sstl implemen- tation. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-14 appendix a. hdl attributes for synplify and precision rtl synthesis using these hdl attributes, you can assign sysio attributes directly in your source. you will need to use the attribute de?ition and syntax for the synthesis vendor you are planning to use. below are a list of all the sysio attributes syntax and examples for precision rtl synthesis and synplify. this section only lists the sysio buffer attributes for these devices. you can refer to the precision rtl synthesis and synplify user manuals for a complete list of synthesis attributes. these manuals are available through isplever software help. vhdl synplify/precision rtl synthesis this section lists syntax and examples for all the sysio attributes in vhdl when using precision rtl synthesis or synplicity synthesis tools. syntax table 8-8. vhdl attribute syntax for synplify and precision rtl synthesis examples io_type --***attribute declaration*** attribute io_type: string; --***io_type assignment for i/o pin*** attribute io_type of porta: signal is ?ci33? attribute io_type of portb: signal is ?vcmos33? attribute io_type of portc: signal is ?vds25? attribute syntax io_type attribute io_type: string; attribute io_type of pinname: signal is ?o_type value? opendrain attribute opendrain: string; attribute opendrain of pinname: signal is ?pendrain value? drive attribute drive: string; attribute drive of pinname: signal is ?rive value? pullmode attribute pullmode: string; attribute pullmode of pinname: signal is ?ullmode value? pciclamp attribute pciclamp: string; attribute pciclamp of pinname: signal is ?ciclamp value? slewrate attribute pullmode: string; attribute pullmode of pinname: signal is ?lewrate value? fixeddelay attribute fixeddelay: string; attribute fixeddelay of pinname: signal is ?ixeddelay value? din attribute din: string; attribute din of pinname: signal is ?? dout attribute dout: string; attribute dout of pinname: signal is ?? loc attribute loc: string; attribute loc of pinname: signal is ?in_locations?
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-15 opendrain --***attribute declaration*** attribute opendrain: string; --***drive assignment for i/o pin*** attribute opendrain of portb: signal is "on"; drive --***attribute declaration*** attribute drive: string; --***drive assignment for i/o pin*** attribute drive of portb: signal is ?0? pullmode --***attribute declaration*** attribute pullmode : string; --***pullmode assignment for i/o pin*** attribute pullmode of porta: signal is "down"; attribute pullmode of portb: signal is "up"; pciclamp --***attribute declaration*** attribute pciclamp: string; --***pullmode assignment for i/o pin*** attribute pciclamp of porta: signal is "on"; slewrate --***attribute declaration*** attribute slewrate : string; --*** slewrate assignment for i/o pin*** attribute slewrate of portb: signal is ?ast? fixeddelay --***attribute declaration*** attribute fixeddelay: string; --*** slewrate assignment for i/o pin*** attribute fixeddelay of portb: signal is ?rue?
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-16 din/dout --***attribute declaration*** attribute din : string; attribute dout : string; --*** din/dout assignment for i/o pin*** attribute din of input_vector: signal is ?? attribute dout of output_vector: signal is ?? loc --***attribute declaration*** attribute loc : string; --*** loc assignment for i/o pin*** attribute loc of input_vector: signal is ?3,b3,c3 ?
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-17 verilog for synplify this section lists syntax and examples for all the sysio attributes in verilog using the synplify synthesis tool. syntax table 8-9. verilog synplify attribute syntax examples //io_type, pullmode, slewrate and drive assignment output portb /*synthesis io_type="lvcmos33" pullmode =?p slewrate =?ast drive =?0?/; output portc /*synthesis io_type="lvds25" */; //opendrain output porta /*synthesis opendrain =?n?/; //pciclamp output porta /*synthesis io_type="pci33" pullmode =?ciclamp?/; // fixeddelay input load /* synthesis fixeddelay="true" */; // place the ?p-?ps near the load input input load /* synthesis din= */; // place the ?p-?ps near the outload output output outload /* synthesis dout= */; attribute syntax io_type pintype pinname /* synthesis io_type=?o_type value?/; opendrain pintype pinname /* synthesis opendrain =?pendrain value?/; drive pintype pinname /* synthesis drive=?rive value?/; pullmode pintype pinname /* synthesis pullmode=?ullmode value?/; pciclamp pintype pinname /* synthesis pciclamp = pciclamp value?/; slewrate pintype pinname /* synthesis slewrate=?lewrate value?/; fixeddelay pintype pinname /* synthesis fixeddelay=?ixeddelay value?/; din pintype pinname /* synthesis din= ?/; dout pintype pinname /* synthesis dout= ?/; loc pintype pinname /* synthesis loc=?in_locations ?/;
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-18 //i/o pin location input [3:0] data0 /* synthesis loc=?3,b1,f3?/; //register pin location reg data_in_ch1_buf_reg3 /* synthesis loc=?40c47 */; //vectored internal bus reg [3:0] data_in_ch1_reg /*synthesis loc =?40c47,r40c46,r40c45,r40c44 */;
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-19 verilog for precision rtl synthesis this section lists syntax and examples for all the sysio attributes in verilog using the precision rtl synthesis syn- thesis tool. syntax table 8-10. verilog precision rtl synthesis attribute syntax example //****io_type *** //pragma attribute porta io_type pci33 //pragma attribute portb io_type lvcmos33 //pragma attribute portc io_type sstl25_ii //*** opendrain *** //pragma attribute portb opendrain on //pragma attribute portd opendrain off //*** drive *** //pragma attribute portb drive 20 //pragma attribute portd drive 8 //*** pullmode*** //pragma attribute portb pullmode up //*** pciclamp*** //pragma attribute portb pciclamp on //*** slewrate *** //pragma attribute portb slewrate fast //pragma attribute portd slewrate slow attribute syntax io_type //pragma attribute pinname io_type io_type value opendrain //pragma attribute pinname opendrain opendrain value drive //pragma attribute pinname drive drive value pullmode //pragma attribute pinname io_type pullmode value pciclamp //pragma attribute pinname pciclamp pciclamp value slewrate //pragma attribute pinname io_type slewrate value fixeddelay //pragma attribute pinname io_type fixeddelay value loc //pragma attribute pinname loc pin_location
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-20 // ***fixeddelay*** // pragma attribute load fixeddelay true //***loc*** //pragma attribute portb loc e3
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-21 appendix b. sysio attributes using preference editor user interface you can also assign the sysio buffer attributes using the pre map preference editor gui available in the isplever tools. the pin attribute sheet list all the ports in your design and all the available sysio attributes as preferences. clicking on each of these cells will produce a list of all the valid i/o preference for that port. each column takes pre- cedence over the next. hence, when a particular io_type is chosen, the drive, pullmode and slewrate columns will only list the valid combinations for that io_type. the user can lock the pin locations using the pin location column of the pin attribute sheet. right-clicking on a cell will list all the available pin locations. the prefer- ence editor will also conduct a drc check to look for incorrect pin assignments. you can enter the din/ dout preferences using the cell attributes sheet of the preference editor. all the prefer- ences assigned using the preference editor are written into the logical preference ?e (.lpf). figure 8-4 and figure 8-5 show the pin attribute sheet and the cell attribute sheet views of the preference editor. for further information on how to use the preference editor, refer to the isplever help documentation located in the help menu option of the software. figure 8-4. pin attributes tab figure 8-5. cell attributes tab
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-22 appendix c. sysio attributes using preference file (ascii file) you can also enter the sysio attributes directly in the preference (.prf) ?e as sysio buffer preferences. the prf ?e is an ascii ?e containing two sections: a schematic section for preferences created by the mapper or translator, and a user section for preferences entered by the user. you can write user preferences directly into this ?e. the synthesis attributes appear between the schematic start and schematic end of the ?e. you can enter the sysio buffer preferences after the schematic end line using the preference ?e syntax. below are a list of sysio buffer preference syntax and examples. iobuf this preference is used to assign the attribute io_type, pullmode, slewrate and drive. syntax iobuf [allports | port | group ] (keyword=)+; where: = these are not the actual top-level port names, but should be the signal name attached to the port. pios in the physical design (.ncd) ?e are named using this convention. any multiple listings or wildcarding should be done using groups keyword = io_type, opendrain, drive, pullmode, pciclamp, slewrate. example iobuf port "port1" io_type=lvttl33 opendrain=on drive=8 pullmode=up pciclamp =off slewrate=fast; define group "bank1" "in*" "out_[0-31]"; iobuf group "bank1" io_type=sstl18_ii; locate when this preference is applied to a speci?d component it places the component at a speci?d site and locks the component to the site. if applied to a speci?d macro instance it places the macros reference component at a speci?d site, places all of the macros pre-placed components (that is, all components that were placed in the macros library ?e) in sites relative to the reference component, and locks all of these placed components at their sites. this can also be applied to a speci?d pgroup. syntax locate [comp | macro ] site ; locate pgroup [site ; | region ;] locate pgroup range [ | ] [] | range []; locate bus < bus_name> row|col ; := string := integer note: if the comp_name, macro_name, or site_name begins with anything other than an alpha character (for exam- ple, ?1c7?, you must enclose the name in quotes. wildcard expressions are allowed in . example this command places the port clk0 on the site a4:
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-23 locate comp ?lk0 site ?4? this command places the component pfu1 on the site named r1c7: locate comp ?fu1 site ?1c7? this command places bus1 on row 3 and bus2 on col4 locate bus ?us1 row 3; locate bus ?us2 col 4; use din cell this preference speci?s the given register to be used as an input flip flop. syntax use din cell ; where: := string example use din cell ?in0? use dout cell speci?s the given register to be used as an output flip flop. syntax use dout cell ; where: := string examples use dout cell ?out1? pgroup vref this preference is used to group all the components that need to be associated to one vref pin within a bank. syntax pgroup [(vref )+] (comp )+; locate pgroup bank ; locate vref site ; example pgroup ?ref_pg1 vref ?ef1 comp ?h(0) comp ?h(1) comp ?h(2) comp ?h(3) comp ?h(4) comp ?h(5) comp ?h(6) comp ?h(7)? pgroup ?ref_pg2 vref ?ef2 comp ?l(0) comp ?l(1) comp ?l(2) comp ?l(3) comp ?l(4) comp ?l(5) comp ?l(6) comp ?l(7)? locate vref ?ef1 site pr29c;
latticeecp/ec and latticexp lattice semiconductor sysio usage guide 8-24 locate vref ?ef2 site pr48b; or locate pgroup ?vref_pg1 bank 2; locate pgroup ?vref_pg2 bank 2;
october 2006 technical note tn1051 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 9-1 tn1051_01.8 introduction this technical note discusses memory usage in the latticeec, latticeecp and latticexp device families. it is intended to be used as a guide for integrating the ebr and pfu based memories for these device families using the isplever design tool. the architecture of the latticeecp/ec and latticexp devices provides a large amount of resources for memory intensive applications. the sysmem embedded block ram (ebr) complements its distributed pfu-based mem- ory. single-port ram, dual-port ram, pseudo dual-port ram and rom memories can be constructed using the ebr. luts and pfu can implement distributed single-port ram, dual-port ram and rom. the internal logic of the device can be used to con?ure the memory elements as fifo and other storage types. the capabilities of the ebr block ram and pfu ram are referred to as primitives and described later in this doc- ument. designers can generate the memory primitives using the ipexpress tool in the isplever software. the ipexpress gui allows users to specify the memory type and size required. ipexpress takes this speci?ation and constructs a netlist to implement the desired memory by using one or more of the memory primitives. the remainder of this document discusses how to utilize ipexpress, memory modules and memory primitives. memories in latticeecp/ec and latticexp devices the latticeecp/ec and latticexp architectures contain an array of logic blocks called pfus or pffs surrounded by programmable i/o cells (pics). interspersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) as shown in figures 9-1, 9-2 and 9-3. the pfu contains the building blocks for logic, and distributed ram and rom. the pff provides the logic building blocks without the distributed ram this document describes the memory usage and implementation for both embedded memory blocks (ebr) and distributed ram of the pfu. refer to the device data sheet for details on the hardware implementation of the ebr and distributed ram. the logic blocks are arranged in a two-dimensional grid with rows and columns as shown in the ?ures below. the physical location of the ebr and distributed ram follows the row and column designation. the distributed ram, since it is part of the pfu resource, follows the pfu/pff row and column designation. the ebr occupies two col- umns per block to account for the wider port interface. memory usage guide for latticeecp/ec and latticexp devices
9-2 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-1. simpli?d block diagram, latticeec device (top level) figure 9-2. simpli?d block diagram, latticeecp device (top level) programmable i/o cell (pic) includes sysio interface sysconfig programming port (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (fast pfu without ram/rom) jtag port sysmem embedded block ram (ebr) programmable i/o cell (pic) includes sysio interface sysconfig programming port (includes dedicated and dual use pins) programmable functional unit (pfu) sysdsp block sysclock pll pff (fast pfu without ram/rom) jtag port sysmem embedded block ram (ebr)
9-3 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-3. simpli?d block diagram, latticexp device (top level) utilizing ipexpress designers can utilize ipexpress to easily specify a variety of memories in their designs. these modules will be con- structed using one or more memory primitives along with general purpose routing and luts as required. the avail- able modules are: single port ram (ram_dq) ?ebr based dual port ram (ram_dp_true) ?ebr based pseudo dual port ram (ram_dp) ?ebr based read only memory (rom) ?ebr based first in first out memory (fifo and fifo_dc) ?ebr based distributed single port ram (distributed_spram) ?pfu based distributed dual port ram (distributed_dpram) ?pfu based distributed rom (distributed_rom) ?pfu/pff based ipexpress flow for generating any of these memories, create (or open) a project for the latticeecp/ec or latticexp devices. from the project navigator, select tools > ipexpress . alternatively, users can also click on the button in the toolbar when the latticeecp/ec and latticexp devices are targeted in the project. this opens the ipexpress window as shown in figure 9-4. programmable i/o cell (pic) includes sysio interface non-volatile memory sysconfig programming port (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (pfu without ram) jtag port sysmem embedded block ram (ebr)
9-4 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-4. ipexpress - main window the left pane of this window has the module tree. the ebr-based memory modules are under the module > memory- module > distributed ram and ebr_components and the pfu-based distributed memory modules are under storage_components as shown in figure 9-4. let us look at an example of the generating an ebr-based pseudo dual port ram of size 512 x 16. select ram_dp under the ebr_components. the right pane changes, as shown in figure 9-5.
9-5 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-5. example generating pseudo dual port ram (ram_dp) using ipexpress in the right-hand pane, options like macro type , version , and module_name are device and selected module dependent. these cannot be changed in ipexpress. users can change the directory where the generated module ?es will be placed by clicking the browse button in the project path . the file name text box allows users to specify the entity and ?e name for the module they are about to generate. users must provide this name. design entry , verilog or vhdl, by default is the same as the project type. if the project is a vhdl project, the selected design entry option will be ?chematic/ vhdl? and ?chematic/ verilog-hdl if the project type is verilog- hdl. then click the customize button. this opens another window where the ram can be customized. the the left-hand side of this window shows the block diagram of the module. the right-hand side includes the con- ?uration tab.
9-6 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-6. generating pseudo dual port ram (ram_dp) module customization ?con?uration tab users can specify the address depth and data width for the read port and the write port in the text boxes pro- vided. in this example we are generating a pseudo dual port ram of size 512 x 16. users can also create rams of different port widths in the case of pseudo dual port and true dual port rams. the check box enable output registers inserts the output registers in the read data port, as the output registers are optional for the ebr-based rams. the reset mode can be selected to be asynchronous reset or synchronous reset. gsr or global set reset can be checked to be enabled or disabled. the input data and the address control is always registered, as the hardware only supports synchronous opera- tion for the ebr based rams users can also pre-initialize their memory with the contents they specify in the memory ?e. it is optional to provide this ?e in the rams. however, in the case of rom, it is required to provide the memory ?e. these ?es can be of binary, hex or addresses hex format. the details of these formats are discussed in the initialization file section of this technical note. at this point, users can click the generate button to generate the module that they have customized. a netlist in the desired format is then generated and placed in the speci?d location. users can incorporate this netlist in their designs. users can check the import lpc to isplever project check box to automatically import the ?e in the project nav- igator. once the module is generated, users can either instantiate the *.lpc or the verilog-hdl/ vhdl ?e in the top level module of their design. the various memory modules, both ebr and distributed, are discussed in detail later in this document.
9-7 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices memory modules single port ram (ram_dq) ?ebr based the ebr blocks in the latticeecp/ec and latticexp devices can be con?ured as single port ram or ram_dq. ipexpress allows users to generate the verilog-hdl or vhdl along an edif netlist for the memory size as per the design requirements. ipexpress generates the memory module as shown in figure 9-7. figure 9-7. single port memory module generated by ipexpress since the device has a number of ebr blocks, the generated module makes use of these ebr blocks or primitives and cascades them to create the memory sizes speci?d by the user in the ipexpress gui. for memory sizes smaller than an ebr block, the module will be created in one ebr block. in cases where the speci?d memory is larger than one ebr block, multiple ebr block can be cascaded, in depth or width (as required to create these sizes). the memory primitive for ram_dq for latticeecp/ec and latticexp devices is shown in figure 9-8. figure 9-8. single port ram primitive or ram_dq for latticeecp/ec and latticexp devices in single port ram mode the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered. ram_dq ebr-based single port memory clock clocken reset we address data q ad[x:0] di[y:0] clk ce rst we do[y:0] cs[2:0] ebr
9-8 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices the various ports and their de?itions for the single port memory are included in table 9-1. the table lists the cor- responding ports for the module generated by ipexpress and for the ebr ram_dq primitive. table 9-1. ebr-based single port memory port de?itions reset (or rst) only resets the input and output registers of the ram. it does not reset the contents of the memory. cs, or chip select, a port available in the ebr primitive, is useful when memory requires multiple ebr blocks to be cascaded. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can easily cascade eight memories. if the memory size speci?d by the user requires more than eight ebr blocks, the software automatically generates the additional address decoding logic which is implemented in the pfu (external to the ebr blocks). each ebr block consists of 9,216 bits of ram. the values for x (for address) and y (data) for each ebr block for the devices are included in table 9-2. table 9-2. single port memory sizes for 9k memories for latticeecp/ec devices table 9-3 shows the various attributes available for the single port memory (ram_dq). some of these attributes are user selectable through the ipexpress gui. for detailed attribute de?itions, refer to appendix a. table 9-3. single port ram attributes for latticeecp/ec devices port name in generated module port name in the ebr block primitive description active state clock clk clock rising clock edge clocken ce clock enable active high address ad[x:0] address bus data di[y:0] data in q do[y:0] data out we we write enable active high reset rst reset active high cs[2:0] chip select single port memory size input data output data address [msb:lsb] 8k x 1 di do ad[12:0] 4k x 2 di[1:0] do[1:0] ad[11:0] 2k x 4 di[3:0] do[3:0] ad[10:0] 1k x 9 di[8:0] do[8:0] ad[9:0] 512 x 18 di[17:0] do[17:0] ad[8:0] 256 x 36 di[35:0] do[35:0] ad[7:0] attribute description values default value user selectable through ipexpress data_width data word width 1, 2, 4, 9, 18, 36 1 yes regmode register mode (pipelining) noreg, outreg noreg yes resetmode selects the reset type async, sync async yes csdecode chip select decode 000, 001, 010, 011, 100, 101, 110, 111 000 no writemode read / write mode normal, writethrough, readbeforewrite normal yes gsr global set reset enabled, disabled enabled yes
9-9 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices the single port ram (ram_dq) can be con?ured as normal, read before write or write through modes. each of these modes affects what data comes out of the port q of the memory during the write operation followed by the read operation at the same memory location. the read before write attribute is supported for x9, x18 and x36 data widths. additionally users can select to enable the output registers for ram_dq. figures 8-7 through 8-12 show the inter- nal timing waveforms for the single port ram (ram_dq) with these options. figure 9-9. single port ram timing waveform ?normal mode, without output registers add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_1 data_2
9-10 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-10. single port ram timing waveform ?normal mode, with output registers figure 9-11. single port ram timing waveform ?read before write mode, without output registers add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 data_1 clock reset wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr add_0 add_0 add_1 add_1 add_2 new data_0 new data_1 invalid data new_data_0 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr old_data_1 old_data_0 new_data_1
9-11 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-12. single port ram timing waveform ?read before write mode, with output registers figure 9-13. single port ram timing waveform ?write through mode, without output registers add_0 add_0 add_1 add_1 add_2 new data_0 new data_1 invalid data new_data_0 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr old_data_1 old_data_0 new data_1 reset add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_2 data_0 data_3 data_4
9-12 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-14. single port ram timing waveform ?write through mode, with output registers add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 reset
9-13 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices true dual port ram (ram_dp_true) ?ebr based the ebr blocks in the latticeecp/ec and latticexp devices can be con?ured as true-dual port ram or ram_dp_true. ipexpress allows users to generate the verilog-hdl, vhdl or edif netlists for the memory size as per design requirements. ipexpress generates the memory module as shown in figure 9-15. figure 9-15. true dual port memory module generated by ipexpress the generated module makes use of the ram_dp_true primitive. for memory sizes smaller than one ebr block, the module will be created in one ebr block. in cases where the speci?d memory is larger than one ebr block, multiple ebr blocks can be cascaded, in depth or width (as required to create these sizes). the basic memory primitive for the latticeecp/ec and latticexp devices, ram_dp_true, is shown in figure 9- 16. figure 9-16. true dual port ram primitive or ram_dp_true for latticeecp/ec and latticexp devices in true dual port ram mode, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. ram_dp_true ebr-based true dual port memory clocka clockena reseta wea wraddressa dataa qa clockb clockenb resetb web wraddressb datab qb ada[x:0] dia[y:0] clka cea rsta wea csa[2:0] ebr doa[y:0] adb[x:0] dib[y:0] clkb ceb rstb web csb[2:0] dob[y:0]
9-14 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices the various ports and their de?itions for the true dual memory are included in table 9-4. the table lists the corre- sponding ports for the module generated by ipexpress and for the ebr ram_dp_true primitive. table 9-4. ebr-based true dual port memory port de?itions reset (or rst) only resets the input and output registers of the ram. it does not reset the contents of the memory. cs, or chip select, a port available in the ebr primitive, is useful when memory requires multiple ebr blocks to be cascaded. the cs signal would form the msb for the address when multiple ebr blocks are cascaded. cs is a 3- bit bus, so it can easily cascade eight memories. however, if the memory size speci?d by the user requires more than eight ebr blocks, the software automatically generates the additional address decoding logic, which is imple- mented in the pfu external to the ebr blocks. each ebr block consists of 9,216 bits of ram. the values for x (for address) and y (data) for each ebr block for the devices are included in table 9-5. table 9-5. true dual port memory sizes for 9k memory for latticeecp/ec and latticexp devices table 9-6 shows the various attributes available for true dual port memory (ram_dp_true). some of these attributes are user selectable through the ipexpress gui. for detailed attribute de?itions, refer to appendix a. port name in generated module port name in the ebr block primitive description active state clocka, clockb clka, clkb clock for porta and portb rising clock edge clockena, clockenb cea, ceb clock enables for port clka and clkb active high addressa, addressb ada[x:0], adb[x:0] address bus port a and port b dataa, datab dia[y:0], dib[y:0] input data port a and port b qa, qb doa[y:0], dob[y:0] output data port a and port b wea, web wea, web write enable port a and port b active high reseta, resetb rsta, rstb reset for port a and port b active high csa[2:0], csb[2:0] chip selects for each port dual port memory size input data port a input data port b output data port a output data port b address port a [msb:lsb] address port b [msb:lsb] 8k x 1 dia dib doa dob ada[12:0] adb[12:0] 4k x 2 dia[1:0] dib[1:0] doa[1:0] dob[1:0] ada[11:0] adb[11:0] 2k x 4 dia[3:0] dib[3:0] doa[3:0] dob[3:0] ada[10:0] adb[10:0] 1k x 9 dia[8:0] dib[8:0] doa[8:0] dob[8:0] ada[9:0] adb[9:0] 512 x 18 dia[17:0] dib[17:0] doa[17:0] dob[17:0] ada[8:0] adb[8:0]
9-15 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices table 9-6. true dual port ram attributes for latticeecp/ec and latticexp the true dual port ram (ram_dp_true) can be con?ured as normal, read before write or write through modes. each of these modes affects what data comes out of the port q of the memory during the write operation followed by the read operation at the same memory location. the read before write attribute is supported for x9 and x18 data widths. detailed discussions of the write modes and the constraints of the true dual port can be found in appendix a. additionally users can select to enable the output registers for ram_dp_true. figures 8-15 through 8-20 show the internal timing waveforms for the true dual port ram (ram_dp_true) with these options. attribute description values default value user selectable through ipexpress data_width_a data word width port a 1, 2, 4, 9, 18 1 yes data_width_b data word width port b 1, 2, 4, 9, 18 1 yes regmode_a register mode (pipelining) for port a noreg, outreg noreg yes regmode_b register mode (pipelining) for port b noreg, outreg noreg yes resetmode selects the reset type async, sync async yes csdecode_a chip select decode for port a 000, 001, 010, 011, 100, 101, 110, 111 000 no csdecode_b chip select decode for port b 000, 001, 010, 011, 100, 101, 110, 111 000 no writemode_a read / write mode for port a normal, writethrough, readbeforewrite normal yes writemode_b read / write mode for port b normal, writethrough, readbeforewrite normal yes gsr global set reset enabled, disabled enabled yes
9-16 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-17. true dual port ram timing waveform ?normal mode, without output registers add_a0 add_a1 add_a0 add_a1 add_a2 data_a0 data_a1 invalid data data_a0 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_a1 data_a2 add_b0 add_b1 add_b0 add_b1 add_b2 data_b0 data_b1 invalid data data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_b1 data_b2
9-17 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-18. true dual port ram timing waveform ?normal mode with output registers add_a0 add_a1 add_a0 add_a1 add_a2 data_a0 data_a1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr add_b0 add_b1 add_b0 add_b1 add_b2 data_b0 data_b1 invalid data data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_b1 invalid data data_a0 t coo_ebr data_a1 reset
9-18 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-19. true dual port ram timing waveform ?read before write mode, without output registers add_a0 add_a0 add_a1 add_a1 add_a2 new data_a0 new data_a1 invalid data new_data_a0 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr old_data_a1 old_data_a0 new_data_a1 add_b0 add_b0 add_b1 add_b1 add_b2 new data_b0 new data_b1 invalid data new_data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr old_data_b1 old_data_b0 new_data_b1 reset
9-19 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-20. true dual port ram timing waveform ?read before write mode, with output registers add_a0 add_a0 add_a1 add_a1 add_a2 new data_a0 new data_a1 invalid data new_data_a0 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr old_data_a1 old_data_a0 new data_a1 add_b0 add_b0 add_b1 add_b1 add_b2 new data_b0 new data_b1 invalid data new_data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr old_data_b1 old_data_b0 new data_b1
9-20 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-21. true dual port ram timing waveform ?write through mode, without output registers add_a0 add_a1 add_a0 data_a0 data_a1 data_a2 data_a3 data_a4 invalid data data_a1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_a2 data_a0 data_a3 data_a4 add_b0 add_b1 add_b0 data_b0 data_b1 data_b2 data_b3 data_b4 invalid data data_b1 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_b2 data_b0 data_b3 data_b4
9-21 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-22. true dual port ram timing waveform ?write through mode, with output registers add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 reset
9-22 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices pseudo dual port ram (ram_dp) ?ebr-based the ebr blocks in the latticeecp/ec and latticexp devices can be con?ured as pseudo-dual port ram or ram_dp. ipexpress allows users to generate the verilog-hdl or vhdl along with an edif netlist for the memory size as per design requirements. ipexpress generates the memory module, as shown in figure 9-23. figure 9-23. pseudo dual port memory module generated by ipexpress the generated module makes use of these ebr blocks or primitives. for memory sizes smaller than an ebr block, the module will be created in one ebr block. if the speci?d memory is larger than one ebr block, multiple ebr block can be cascaded, in depth or width (as required to create these sizes). the basic pseudo dual port memory primitive for the latticeecp/ec and latticexp devices is shown in figure 9- 24. figure 9-24. pseudo dual port ram primitive or ram_dp for latticeecp/ec and latticexp devices in the pseudo dual port ram mode, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. the various ports and their de?itions for the single port memory are included in table 9-7. the table lists the cor- responding ports for the module generated by ipexpress and for the ebr ram_dp primitive. ram_dp ebr based pseudo dual port memory wrclock wrclocken reset we wraddress data rdclock rdclocken rdaddress q adw[x:0] di[y:0] clkw cew rst we cs[2:0] ebr adr[x:0] clkr cer do[y:0]
9-23 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices table 9-7. ebr based pseudo-dual port memory port de?itions reset (or rst) only resets the input and output registers of the ram. it does not reset the contents of the memory. cs, or chip select, a port available in the ebr primitive, is useful when memory requires multiple ebr blocks to be cascaded. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can cascade eight memories easily. however, if the memory size speci?d by the user requires more than eight ebr blocks, the software automatically generates the additional address decoding logic, which is imple- mented in the pfu (external to the ebr blocks). each ebr block consists of 9,216 bits of ram. the values for x (for address) and y (data) for each ebr block for the devices are included in table 9-8. table 9-8. pseudo-dual port memory sizes for 9k memory for latticeecp/ec and latticexp devices table 9-9 shows the various attributes available for the pseudo dual port memory (ram_dp). some of these attributes are user selectable through the ipexpress gui. for detailed attribute de?itions, refer to appendix a. port name in generated module port name in the ebr block primitive description active state rdaddress adr[x:0] read address wraddress adw[x:0] write address rdclock clkr read clock rising clock edge wrclock clkw write clock rising clock edge rdclocken cer read clock enable active high wrclocken cew write clock enable active high q do[y:0] read data data di[y:0] write data we we write enable active high reset rst reset active high cs[2:0] chip select pseudo-dual port memory size input data port a input data port b output data port a output data port b read address port a [msb:lsb] write address port b [msb:lsb] 8k x 1 dia dib doa dob rad[12:0] wad[12:0] 4k x 2 dia[1:0] dib[1:0] doa[1:0] dob[1:0] rad[11:0] wad[11:0] 2k x 4 dia[3:0] dib[3:0] doa[3:0] dob[3:0] rad[10:0] wad[10:0] 1k x 9 dia[8:0] dib[8:0] doa[8:0] dob[8:0] rad[9:0] wad[9:0] 512 x 18 dia[17:0] dib[17:0] doa[17:0] dob[17:0] rad[9:0] wad[9:0]
9-24 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices table 9-9. pseudo-dual port ram attributes for latticeecp/ec and latticexp devices users have the option of enabling the output registers for pseudo-dual port ram (ram_dp). figures 8-23 and 8- 24 show the internal timing waveforms for the pseudo-dual port ram (ram_dp) with these options. figure 9-25. pseudo dual port ram timing diagram ?without output registers attribute description values default value user selectable through ipexpress data_width_w write data word width 1, 2, 4, 9, 18, 36 1 yes data_width_r read data word width 1, 2, 4, 9, 18, 36 1 yes regmode register mode (pipelining) noreg, outreg noreg yes resetmode selects the reset type async, sync async yes csdecode_w chip select decode for write 000, 001, 010, 011, 100, 101, 110, 111 000 no csdecode_r chip select decode for read 000, 001, 010, 011, 100, 101, 110, 111 000 no gsr global set reset enabled, disabled enabled yes data_0 data_1 data_2 invalid data data_0 wrclock data q wrclocken t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_1 dat a_2 add_0 add_1 add_2 rdaddress t suaddr_ebr t haddr_ebr rdclock rdclocken t suce_ebr t hce_ebr add_0 add_1 add_2 wraddress t suaddr_ebr t haddr_ebr
9-25 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-26. pseudo dual port ram timing diagram ?with output registers read only memory (rom) ?ebr based the ebr blocks in the latticeecp/ec and latticexp devices can be con?ured as read only memory or rom. ipexpress allows users to generate the verilog-hdl or vhdl along with an edif netlist for the memory size as per design requirements. users are required to provide the rom memory content in the form of an initialization ?e. ipexpress generates the memory module as shown in figure 9-27. figure 9-27. rom - read only memory module generated by ipexpress the generated module makes use of these ebr blocks or primitives. for memory sizes smaller than an ebr block, the module will be created in one ebr block. if the speci?d memory is larger than one ebr block, multiple ebr blocks can be cascaded, in depth or width (as required to create these sizes). the basic rom primitive for the latticeecp/ec and latticexp devices is as shown in figure 9-28. data_0 data_1 data_2 invalid data data_0 wrclock data q wrclocken t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr dat a_1 add_0 add_1 add_2 rdaddress t suaddr_ebr t haddr_ebr rdclock rdclocken t suce_ebr t hce_ebr add_0 add_1 add_2 wraddress t suaddr_ebr t haddr_ebr rom ebr based read only memory outclock outclocken reset address q
9-26 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-28. rom primitive for latticeecp/ec and latticexp devices in the rom mode the address for the port is registered at the input of the memory array. the output data of the memory is optionally registered at the output. the various ports and their de?itions for the rom are included in table 9-10. the table lists the corresponding ports for the module generated by ipexpress and for the rom primitive. table 9-10. ebr-based rom port de?itions reset (or rst) only resets the input and output registers of the ram. it does not reset the contents of the memory. cs, or chip select, a port available in the ebr primitive, is useful when memory requires multiple ebr blocks to be cascaded. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can cascade eight memories easily. however, if the memory size speci?d by the user requires more than eight ebr blocks, the software automatically generates the additional address decoding logic, which is imple- mented in the pfu (external to the ebr blocks). while generating the rom using ipexpress, the user is required to provide an initialization ?e to pre-initialize the contents of the rom. these ?e are the *.mem ?es and they can be of binary, hex or the addressed hex formats. the initialization ?es are discussed in detail in the initializing memory section of this technical note. users have the option of enabling the output registers for read only memory (rom). figures 8-27 and 8-28 show the internal timing waveforms for the read only memory (rom) with these options. port name in generated module port name in the ebr block primitive description active state address ad[x:0] read address outclock clk clock rising clock edge outclocken ce clock enable active high reset rst reset active high cs[2:0] chip select ad[x:0] clk ce ebr do[y:0] rst cs[2:0]
9-27 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-29. rom timing waveform ?without output registers figure 9-30. rom timing waveform ?with output registers add_0 add_1 add_2 add_3 add_4 invalid data data_0 outclock address q outclocken t suaddr_ebr t haddr_ebr t suce_ebr t hce_ebr t co_ebr data_1 data_2 data_3 data_4 add_0 add_1 add_2 add_3 add_4 invalid data data_0 outclock address q outclocken t suaddr_ebr t haddr_ebr t suce_ebr t hce_ebr t coo_ebr data_1 data_2 data_3
9-28 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices first in first out (fifo, fifo_dc) ?ebr based the ebr blocks in the latticeecp/ec and latticexp devices can be con?ured as first in first out memories fifo and fifo_dc. fifo has a common clock for both read and write ports and fifo_dc (or dual clock fifo) has separate clocks for these ports. ipexpress allows users to generate the verilog-hdl or vhdl along with an edif netlist for the memory size as per design requirement. ipexpress generates the fifo and fifo_dc memory module as shown in figures 9-31 and 9-32. figure 9-31. fifo module generated by ipexpress figure 9-32. fifo_dc module generated by ipexpress latticeecp/ec and latticexp devices do not have a built in fifo. these devices have an emulated fifo and fifo_dc. these are emulated by creating a wrapper around the existing rams (like ram_dp). this wrapper also includes address pointer generation and fifo ?g generation logic which will be implemented external to the ebr block. therefore, in addition to the regular ebr usage, there is extra logic for the address pointer generation and fifo ?g generation. a clock is always required as only synchronous write is supported. the various ports and their de?itions for the fifo and fifo_dc are included in table 11. fifo ebr based first-in first-out memory clock wren rden reset q data full almost full empty almost empty fifo ebr based first-in first-out memory wrclock wren rden reset q data full almost full empty almost empty rdclock
9-29 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices table 9-11. ebr-based fifo and fifo_dc memory port de?itions reset (or rst) only resets the output registers of the fifo and fifo_dc. it does not reset the contents of the memory. the various supported sizes for the fifo and fifo_dc in latticeecp/ec and latticexp devices are shown in table 9-12. table 9-12. fifo and fifo_dc data widths sizes for latticeecp/ec and latticexp devices fifo flags the fifo and fifo_dc have four ?gs available: empty, almost empty, almost full and full. the almost empty and almost full ?gs have a programmable range. the program ranges for the four fifo ?gs are speci?d in table 9-13. table 9-13. fifo flag settings the only restriction on the ?g setting is that the values must be in a speci? order (empty=0, almost empty next, followed by almost full and full, respectively). the value of empty is not equal to the value of almost empty (or full is equal to almost full). in this case, a warning is generated and the value of empty (or full) is used in place of almost empty (or almost full). when coming out of reset, the active high flags empty and almost empty are set to high, since they are true. port name in generated module description clk clock (fifo) rising clock edge clkr read port clock (fifo_dc) rising clock edge clkw write port clock (fifo_dc) rising clock edge we write enable active high re read enable active high rst reset active high di data input do data output ff full flag active high af almost full flag active high ef empty flag active high ae almost empty active high fifo size input data output data 8k x 1 di do 4k x 2 di[1:0] do[1:0] 2k x 4 di[3:0] do[3:0] 1k x 9 di[8:0] do[8:0] 512 x 18 di[17:0] do[17:0] 256 x 36 di[35:0] do[35:0] fifo attribute name description programming range program bits ff full ?g setting 2n - 1 14 aff almost full setting 1 to (ff-1) 14 aef almost empty setting 1 to (ff-1) 14 ef empty setting 0 5
9-30 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices the user should specify the absolute value of the address at which the almost empty and almost full flags will go true. for example, if the almost full flag is required to go true at the address location 500 for a fifo of depth 512, the user should specify the value 500 in the ipexpress. the empty and almost empty flags are always registered with the read clock and the full and almost full flags are always registered to the write clock. fifo operation fifos are not supported in the hardware. the hardware has embedded block rams (ebr) which can be con?- ured in single port (ram_dq), pseudo-dual port (ram_dp) and true dual port (ram_dp_true) rams. the fifos in these devices are emulated fifos that are built around these rams. each of these fifos can be con?ured with (pipelined) and without (non-pipelined) output registers. in the pipe- lined mode users have an extra option for these output registers to be enabled by the rden signal. we will discuss the operation in the following sections. let us take a look at the operation of these fifos. first in first out (fifo) memory: the fifo or the single clock fifo is an emulated fifo. the address logic and the ?g logic is implemented in the fpga fabric around the ram. the ports available on the fifo are: reset clock wren rden data ? full flag almost full flag empty flag almost empty flag let us ?st discuss the non-pipelined or the fifo without output registers. figure 9-33 shows the operation of the fifo when it is empty and the data starts to get written into it.
9-31 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-33. fifo without output registers, start of data write cycle the wren signal has to be high to start writing into the fifo. the empty and almost empty ?gs are high to begin and full and almost full are low. when the ?st data gets written into the fifo, the empty ?g de-asserts (or goes low), as the fifo is no longer empty. in this ?ure we are assuming that the almost empty setting ?g setting is 3 (address location 3). so the almost empty ?g gets de-asserted when the 3rd address location gets ?led. now let is assume that we continue to write into the fifo to ?l it. when the fifo is ?led, the almost full and full flags are asserted. figure 9-34 shows the behavior of these ?gs. in this ?ure we assume that fifo depth is ?? data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid q q
9-32 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-34. fifo without output registers, end of data write cycle in this case, as seen above, the almost full ?g is in location 2 before the fifo is ?led. the almost full ?g is asserted when n-2 location is written, and full ?g is asserted when the last word is written into the fifo. data_x data inputs do not get written as the fifo is full (full ?g is high). now let us look at the waveforms when the contents of the fifo are read out. figure 9-35 shows the start of the read cycle. rden goes high and the data read starts. the full and almost full ?gs gets de-asserted as shown. data_n-2 data_n-1 data_n data_x clock reset wren rden data empty almost empty full almost full invalid q q data_x
9-33 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-35. fifo without output registers, start of data read cycle similarly as the data is read out, and fifo is emptied, the almost empty and empty ?gs are asserted. below is the figure 9-36. fifo without output registers, end of data read cycle data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid data q data_n-3 data_n-2 data_n-1 data_n clock reset wren rden data empty almost empty full almost full invalid data q data_n-4
9-34 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figures 9-33 to 9-36 show the behavior of non-pipelined fifo or fifo without output registers. when we pipeline the registers, the output data is delayed by one clock cycle. there is an extra option of output registers being enabled by rden signal. figures 9-37 to 9-40 show the similar waveforms for the fifo with output register and without output register enable with rden. it should be noted that ?gs are asserted and de-asserted with similar timing to the fifo with- out output registers. however it is only the data out 'q' that gets delayed by one clock cycle. figure 9-37. fifo with output registers, start of data write cycle data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid q q
9-35 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-38. fifo with output registers, end of data write cycle figure 9-39. fifo with output registers, start of data read cycle data_n-2 data_n-1 data_n data_x clock reset wren rden data empty almost empty full almost full invalid q q data_x data_1 invalid data data_2 data_3 data_4 clock reset wren rden data empty almost empty full almost full invalid data q
9-36 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-40. fifo with output registers, end of data read cycle and ?ally, if you select the option enable output register with rden, it still delays the data out by one clock cycle (as compared to the non-pipelined fifo), and the rden should be high also during that clock cycle, otherwise the data takes an extra clock cycle when the rden goes true. figure 9-41. fifo with output registers and rden on output registers data_n-4 data_n-3 data_n-2 data_n-1 data_n clock reset wren rden data empty almost empty full almost full invalid data q data_n-5 data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full q data_1 invalid data data_2
9-37 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices dual clock first in first out (fifo_dc) memory: the fifo_dc or the dual clock fifo is also an emulated fifo. again the address logic and the ?g logic is implemented in the fpga fabric around the ram. the ports available on the fifo_dc are: reset rpreset wrclock rdclock wren rden data ? full flag almost full flag empty flag almost empty flag fifo_dc flags: fifo_dc, as an emulated fifo, required the ?gs to be implemented in the fpga logic around the block ram. because of the two clocks, the ?gs are required to change clock domains from read clock to write clock and vice versa. this adds latency to the ?gs either during assertion or during de-assertion. the latency can be avoided only in one of the cases (either assertion or de-assertion). in the current emulated fifo, there is no latency during assertion of these ?gs. thus, when these ?g go true, there is no latency. however this causes the latency during the de-assertion. let us assume that we start to write into the fifo_dc to ?l it. the write operation is controlled by wrclock and wren, however it takes extra rdclock cycles for de-assertion of empty and almost empty ?gs. on the other hand, de-assertion of full and almost full result in reading out the data from the fifo_dc. it takes extra wrclock cycles after reading the data for these ?gs to come out. with this in mind, let us look at the fifo_dc without output register waveforms. figure 9-42 shows the operation of the fifo_dc when it is empty and the data starts to get written into it.
9-38 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-42. fifo_dc without output registers, start of data write cycle the wren signal has to be high to start writing into the fifo_dc. the empty and almost empty ?gs are high to begin and full and almost full are low. when the ?st data gets written into the fifo_dc, the empty ?g de-asserts (or goes low), as the fifo_dc is no longer empty. in this ?ure we are assuming that the almost empty setting ?g setting is 3 (address location 3). so the almost empty ?g gets de-asserted when the third address location gets ?led. now let is assume that we continue to write into the fifo_dc to ?l it. when the fifo_dc is ?led, the almost full and full flags are asserted. figure 9-43 shows the behavior of these ?gs. in this ?ure we assume that fifo_dc depth is ?? data_1 invalid data data_2 data_3 data_4 data_5 wrclock reset wren rden data empty almost empty full almost full invalid q q rdclock rpreset
9-39 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-43. fifo_dc without output registers, end of data write cycle in this case, the almost full ?g is in location 2 before the fifo_dc is ?led. the almost full ?g is asserted when n-2 location is written, and full ?g is asserted when the last word is written into the fifo_dc. data_x data inputs do not get written as the fifo_dc is full (full ?g is high). note that the assertion of these ?gs is immediate and there is no latency when they go true. now let us look at the waveforms when the contents of the fifo_dc are read out. figure 9-44 shows the start of the read cycle. rden goes high and the data read starts. the full and almost full ?gs get de-asserted as shown. in this case, note that the de-assertion is delayed by two clock cycles. wrclock reset empty almost empty full almost full invalid q q rdclock rpreset data_n-2 data_n-1 data_n data_x data_x wren rden data
9-40 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-44. fifo_dc without output registers, start of data read cycle similarly, as the data is read out and fifo_dc is emptied, the almost empty and empty ?gs are asserted. below is the figure 9-45. fifo_dc without output registers, end of data read cycle wrclock reset empty almost empty full almost full invalid data q rdclock rpreset data_1 data_2 invalid q wren rden data data_3 data_6 data_5 data_4 wrclock reset empty almost empty full almost full invalid data q rdclock rpreset wren rden data data_n-2 data_n-1 data_n data_n data_n-3
9-41 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figures 9-42 to 9-45 show the behavior of non-pipelined fifo_dc or fifo_dc without output registers. when we pipeline the registers, the output data is delayed by one clock cycle. there is an extra option for output registers to be enabled by the rden signal. figures 9-46 to 9-49 show similar waveforms for the fifo_dc with output register and without output register enable with rden. it should be noted that ?gs are asserted and de-asserted with similar timing to the fifo_dc without output registers. however it is only the data out ? that is delayed by one clock cycle. figure 9-46. fifo_dc with output registers, start of data write cycle data_1 invalid data data_2 data_3 data_4 data_5 wrclock reset wren rden data empty almost empty full almost full invalid q q rdclock rpreset
9-42 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-47. fifo_dc with output registers, end of data write cycle figure 9-48. fifo_dc with output registers, start of data read cycle wrclock reset empty almost empty full almost full invalid q q rdclock rpreset data_n-2 data_n-1 data_n invalid data invalid data wren rden data wrclock reset empty almost empty full almost full invalid data q rdclock rpreset data_1 invalid q wren rden data data_2 data_5 data_4 data_3
9-43 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-49. fifo_dc with output registers, end of data read cycle finally, if you select the option enable output register with rden, it still delays the data out by one clock cycle (as compared to the non-pipelined fifo_dc), and the rden should be high also during that clock cycle. otherwise the data takes an extra clock cycle when the rden is goes true. figure 9-50. fifo_dc with output registers and rden on output registers wrclock reset empty almost empty full almost full invalid data q rdclock rpreset wren rden data data_n-3 data_n-2 data_1 data_n data_n-4 wrclock reset empty almost empty full almost full invalid data q rdclock rpreset invalid q wren rden data data_3 data_2 data_1
9-44 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices distributed single port ram (distributed_spram) ?pfu based pfu-based distributed single port ram is created using the 4-input lut (look-up table) available in the pfu. these luts can be cascaded to create larger distributed memory sizes. the memorys address and output regis- ters are optional. figure 9-51 shows the distributed single port ram module as generated by the ipexpress. figure 9-51. distributed single port ram module generated by ipexpress the generated module makes use of the 4-input lut available in the pfu. additional logic like clock, clocken and reset is generated by utilizing the resources available in the pfu. the basic distributed single port ram primitive for the latticeecp/ec and latticexp devices is shown in figure 9-52. figure 9-52. distributed single port ram (distributed_spram) for latticeecp/ec and latticexp devices ports such as read clock (rdclock) and read clock enable (rdclocken) are not available in the hardware primi- tive. these are generated by ipexpress when the user wants to enable the output registers in the ipexpress con?- uration. the various ports and their de?itions for the memory are included in table 9-14. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. pfu based distributed single port memory clock clocken reset we address q data ad[3:0] ck wre pfu do[1:0] di[1:0]
9-45 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices table 9-14. pfu based distributed single port ram port de?itions users have an option of enabling the output registers for distributed single port ram (distributed_spram). fig- ures 8-35 and 8-36 show the internal timing waveforms for the distributed single port ram (distributed_spram) with these options. figure 9-53. pfu based distributed single port ram timing waveform - without output registers port name in generated module port name in the ebr block primitive description active state clock ck clock rising clock edge clocken - clock enable active high reset - reset active high we wre write enable active high address ad[3:0] address data di[1:0] data in q do[1:0] data out add_0 add_1 add_0 add_1 add_2 data_0 data_1 in v alid data data_0 clock w e address data q clocken t h w re n _pfu t suaddr_pfu t haddr_pfu t sudata_pfu t hdata_pfu t coram_pfu data_1 t su w re n _pfu data_2
9-46 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-54. pfu based distributed single port ram timing waveform ?with output registers distributed dual port ram (distributed_dpram) ?pfu based pfu-based distributed dual port ram is also created using the four input lut (look-up table) available in the pfu. these luts can be cascaded to create larger distributed memory sizes. figure 9-55 shows the distributed single port ram module as generated by ipexpress. figure 9-55. distributed dual port ram module generated by ipexpress the generated module makes use of a 4-input lut available in the pfu. additional logic for clocks, clock enables and reset is generated by utilizing the resources available in the pfu. the basic distributed dual port ram primi- tive for the latticeecp/ec and latticexp devices is shown in figure 9-56. add_0 add_1 add_0 add_1 add_2 data_0 data_1 in v alid data data_0 clock w e address data q clocken t h w re n _pfu t suaddr_pfu t haddr_pfu t sudata_pfu t hdata_pfu t co? t su w re n _pfu reset data_1 data_2 pfu based distributed dual port memory wraddress rdaddress rdclock rdclocken reset q we wrclock wrclocken data
9-47 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-56. pfu-based distributed dual port ram for latticeecp/ec and latticexp devices ports such as read clock (rdclock) and read clock enable (rdclocken) are not available in the hardware primi- tive. these are generated by ipexpress when the user wants the to enable the output registers in the ipexpress con?uration. the various ports and their de?itions for the memory are included in table 9-15. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. table 9-15. pfu-based distributed dual-port ram port de?itions users have the option of enabling the output registers for distributed dual port ram (distributed_dpram). fig- ures 8-39 and 8-40 show the internal timing waveforms for the distributed dual port ram (distributed_dpram) with these options. port name in generated module port name in ebr block primitive description active state wraddress wad[23:0] write address rdaddress rad[3:0] read address rdclock read clock rising clock edge rdclocken read clock enable active high wrclock wck write clock rising clock edge wrclocken write clock enable active high we wre write enable active high data di[1:0] data input q rdo[1:0] data out wad[3:0] wck wre pfu wdo[1:0] di[1:0] rdo[1:0] rad[3:0]
9-48 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-57. pfu based distributed dual port ram timing waveform - without output registers (non-pipe- lined) data_0 data_1 data_2 in v alid data w rclock data q w rclocken t sudata_ebr t hdata_ebr t coram_pfu t suce_ebr t hce_ebr rdaddress add_0 add_1 add_2 w raddress t suaddr_ebr t haddr_ebr w e add_0 add_1 add_2 data_0 data_1 data_2
9-49 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-58. pfu based distributed dual port ram timing waveform ?with output registers distributed rom (distributed_rom) ?pfu based pfu-based distributed rom is also created using the 4-input lut (look-up table) available in the pfu. these luts can be cascaded to create larger distributed memory sizes. figure 9-59 shows the distributed single port ram module as generated by ipexpress. figure 9-59. distributed rom generated by ipexpress the generated module makes use of the 4-input lut available in the pfu. the basic distributed dual port ram primitive for the latticeecp/ec and latticexp devices is shown in figure 9-60. data_0 data_1 in v alid data data_0 w rclock data q w rclocken t sudata_pfu t hdata_pfu t su w re n _pfu t h w re n _pfu t coram_pfu data_1 add_0 add_1 rdaddress rdclock rdclocken t suce_pfu t hce_pfu add_0 add_1 w raddress t suaddr_pfu t haddr_pfu reset w e t su w re n _pfu t h w re n _pfu pfu-based distributed rom address outclock outclocken reset q
9-50 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-60. pfu-based distributed rom (sync_rom) for latticeecp/ec and latticexp devices ports such as out clock (outclock) and out clock enable (outclocken) are not available in the hardware primi- tive. these are generated by ipexpress when the user wants the to enable the output registers in the ipexpress con?uration. the various ports and their de?itions for the memory are included in table 9-16. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. table 9-16. pfu-based distributed rom port de?itions users have the option of enabling the output registers for distributed rom (distributed_rom). figures 8-43 and 8- 44 show the internal timing waveforms for the distributed rom with these options. figure 9-61. pfu based rom timing waveform ?without output registers port name in generated module port name in the ebr block primitive description active state address ad[3:0] address outclock out clock rising clock edge outclocken out clock enable active high reset reset active high q do data out pfu do a d[3:0] add_0 add_1 add_2 in v alid data data_0 address q t suaddr_pfu t haddr_pfu t coram_pfu data_1 data_2
9-51 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices figure 9-62. pfu based rom timing waveform ?with output registers initializing memory in the ebr based rom or ram memory modes and the pfu based rom memory mode, it is possible to specify the power-on state of each bit in the memory array. each bit in the memory array can have one of two values: 0 or 1. initialization file format the initialization ?e is an ascii ?e, which a user can create or edit using any ascii editor. ipexpress supports three types of memory ?e formats: 1. binary ?e 2. hex file 3. addressed hex the ?e name for the memory initialization ?e is *.mem (.mem). each row depicts the value to be stored in a particular memory location. the number of characters (or the number of columns) represents the num- ber of bits for each address (or the width of the memory module). the initialization file is primarily used for con?uring the roms. the ebr in ram mode can optionally use this ini- tialization file also to preload the memory contents. add_0 add_1 add_2 in v alid data data_0 o u tclock address q o u tclocken t suaddr_pfu t haddr_pfu data_1 reset t coram_pfu
9-52 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices binary file the ?e is essentially a text ?e of 0s and 1s. the rows indicate the number of words and columns indicate the width of the memory. memory size 20x32 00100000010000000010000001000000 00000001000000010000000100000001 00000010000000100000001000000010 00000011000000110000001100000011 00000100000001000000010000000100 00000101000001010000010100000101 00000110000001100000011000000110 00000111000001110000011100000111 00001000010010000000100001001000 00001001010010010000100101001001 00001010010010100000101001001010 00001011010010110000101101001011 00001100000011000000110000001100 00001101001011010000110100101101 00001110001111100000111000111110 00001111001111110000111100111111 00010000000100000001000000010000 00010001000100010001000100010001 00010010000100100001001000010010 00010011000100110001001100010011 hex file the hex ?e is essentially a text ?e of hex characters arranged in a similar row-column arrangement. the number of rows in the ?e is same as the number of address locations, with each row indicating the content of the memory location. memory size 8x16 a001 0b03 1004 ce06 0007 040a 0017 02a4 addressed hex (orca) addressed hex consists of lines of address and data. each line starts with an address, followed by a colon, and any number of data. the format of mem?e is address: data data data data ... where address and data are hexa- decimal numbers. -a0 : 03 f3 3e 4f -b2 : 3b 9f the ?st line puts 03 at address a0, f3 at address a1, 3e at address a2,and 4f at address a3. the second line puts 3b at address b2 and 9f at address b3. there is no limitation on the values of address and data. the value range is automatically checked based on the values of addr_width and data_width. if there is an error in an address or data value, an error message is printed. users need not specify data at all address locations. if data is not speci?d at a certain address, the data at that
9-53 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices location is initialized to 0. ipexpress makes memory initialization possible both through the synthesis and simula- tion ?ws. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history date version change summary june 2004 01.0 initial release. july 2004 01.1 minor updates only. october 2004 01.2 minor updates only. february 2005 01.3 replace latticeec and latticeecp latticeec, latticeecp and latticexp replace latticeecp/eclatticeec/ecp and latticexp replace latticeec or latticeecp latticeec, latticeecp or latticexp added hardware related information for the latticeec/ecp/xp devices update figure 8-4 figure 8-40 replace ?ebr with ?pfu in the ?ures timing parameters. april 2005 01.4 updated the trual dual port ram and module manager flow sections. october 2005 01.5 updated the block diagrams of modules generated by the module manager. added section for module manager ?w example. added section for pmi ?w. february 2006 01.6 removed the pmi support section april 2006 01.7 updated the initializing memory section october 2006 01.8 updated the fifo section. added dual port memory access notes in appendix a.
9-54 memory usage guide lattice semiconductor latticeecp/ec and latticexp devices appendix a. attribute de?itions data_width data width is associated with the ram and fifo elements. the data_width attribute will de?e the number of bits in each word. it takes the values as de?ed in the ram size tables in each memory module. regmode regmode or the register mode attribute is used to enable pipelining in the memory. this attribute is associated with the ram and fifo elements. the regmode attribute takes the noreg or outreg mode parameter that disables and enables the output pipeline registers. resetmode the resetmode attribute allows users to select the mode of reset in the memory. this attribute is associated with the block ram elements. resetmode takes two parameters: sync and async. sync means that the memory reset is synchronized with the clock. async means that the memory reset is asynchronous to clock. csdecode csdecode or the chip select decode attributes are associated to block ram elements. cs, or chip select, is the port available in the ebr primitive that is useful when memory requires multiple ebr blocks cascaded. the cs sig- nal would form the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can cas- cade 8 memories easily. csdecode takes the following parameters: ?00? ?01? ?10? ?11? ?00? ?01? ?10? and ?11? csdecode values determine the decoding value of cs[2:0]. csdecode_w is chip select decode for write and csdecode_r is chip select decode for read for pseudo dual port ram. csdecode_a and csdecode_b are used for true dual port ram elements and refer to the a and b ports. writemode the writemode attribute is associated with the block ram elements. it takes the normal, writethrough, and readbeforewrite mode parameters. in normal mode, the output data does not change or get updated, during the write operation. this mode is sup- ported for all data widths. in writethrough mode, the output data is updated with the input data during the write cycle. this mode is sup- ported for all data widths. in readbeforewrite mode, the output data port is updated with the existing data stored in the write address, during a write cycle. this mode is supported for x9, x18 and x36 data widths. writemode_a and writemode_b are used for dual port ram elements and refer to the a and b ports in case of a true dual port ram. for all modes (of the true dual port module), simultaneous read access from one port and write access from the other port to the same memory address is not recommended. the read data may be unknown in this situation. also, simultaneous write access to the same address from both ports is not recommended. (when this occurs, the data stored in the address becomes undetermined when one port tries to write a 'h' and the other tries to write a 'l'. ) it is recommended that the designer implements control logic to identify this situation if it occurs and either: 1. implement status signals to ?g the read data as possibly invalid, or 2. implement control logic to prevent the simultaneous access from both ports. gsr gsr or global set/ reset attribute is used to enable or disable the global set/reset for ram element.
www.latticesemi.com 10-1 tn1050_03.2 february 2007 technical note tn1050 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. introduction latticeecp, latticeec and latticexp devices support various double data rate (ddr) and single data rate (sdr) interfaces using the logic built into the programmable i/o (pio). sdr applications capture data on one edge of a clock while the ddr interfaces capture data on both the rising and falling edges of the clock, thus dou- bling the performance. this document will address in detail how to utilize the capabilities of the latticeecp/ec and latticexp devices to implement both generic ddr and ddr memory interfaces. ddr sdram interfaces overview ddr sdram interfaces rely on the use of a data strobe signal, called dqs, for high-speed operation. when read- ing data from the external memory device, data coming into the device is edge aligned with respect to the dqs sig- nal. this dqs strobe signal needs to be phase shifted 90 degrees before fpga logic can sample the read data. when writing to a ddr sdram the memory controller (fpga) must shift the dqs by 90 degrees to center align with the data signals (dq). dq and dqs are bi-directional ports. the same two signals are used for both write and read operations. a clock signal is also provided to the memory. this clock is provided as a differential clock (clkp and clkn) to minimize duty cycle variations. the memory also uses these clock signals to generate the dqs sig- nal during a read via a dll inside the memory. the skew between clkp or clkn and the sdram-generated dqs signal is speci?d in the ddr sdram data sheet. figures 10-1 and 10-2 show dq and dqs relationships for read and write cycles. during read, the dqs signal is low for some duration after it comes out of tristate. this state is called preamble. the state when the dqs is low before it goes into tristate is the postamble state. this is the state after the last valid data transition. ddr sdram also require a data mask (dm) signals to mask data bits during write cycles. sdram interfaces typ- ically are implemented with x8, x16 and x32 bits for each dqs signal. note that the ratio of dqs to data bits is independent of the overall width of the memory. an 8-bit interface will have one strobe signal. figure 10-1. typical ddr interface fpga (ddr memory controller) ddr memory dq<7:0> dqs dm address command control clk/clkn dq<7:0> dqs dm address command control clk/clkn dq<7:0> dqs dm address command control clk/clkn 8 x y z latticeecp/ec and latticexp ddr usage guide
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-2 figure 10-2. dq-dqs during read figure 10-3. dq-dqs during write implementing ddr memory interfaces with the latticeecp/ec devices this section describes how to implement the read and write sections of a ddr memory interface. it also provides details of the dq and dqs grouping rules associated with the latticeecp/ec and latticexp devices. dqs grouping each dqs group generally consists of at least 10 i/os (1dqs, 8dq and 1dm) to implement a complete 8-bit ddr memory interface. in the latticeecp/ec devices each dqs signal will span across 16 i/os and in the latticexp devices the dqs will span 14 i/os. any 10 of these 16 i/os can be used to implement an 8-bit ddr memory inter- face. in addition to the dqs grouping, the user must also assign one reference voltage vref1 for a given i/o bank. the tables below show the total number of dqs groups available per i/o bank for each device and package. dqs (at pin) preamble postamble dqs pin to reg and 90 degree phase shift dq (at pin) dqs (at reg) dq (at reg) dqs (at pin) dq (at pin)
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-3 table 10-1. number of dqs banks in the latticeecp/ec device table 10-2. number of dqs banks in the latticexp device package device total x8 dqs groups number of dqs groups per i/o bank 01234567 100-pin tqfp lfec1 3 11001000 lfec3 3 11001000 144-pin tqfp lfec1 6 11011110 lfec3 6 11011110 lfec6/lfecp6 6 11011110 208-pin tqfp lfec1 6 11011110 lfec3 8+2 1 1+1 1 11111+1 1 11 lfec6/lfecp6 8+2 1 1+1 1 11111+1 1 11 lfec10/lfecp10 8+2 1 1+1 1 11111+1 1 11 256-ball fpbga lfec3 10 21111211 lfec6/lfecp6 12 21121221 lfec10/lfecp10 12 21121221 lfec15/lfecp15 12 21121221 484-ball fpbga lfec6/lfecp6 14 22122221 lfec10/lfecp10 18 32222322 lfec15/lfecp15 20 33223322 lfec20/lfecp20 22 33233332 lfec33/lfecp33 22 33233332 672-ball fpbga lfec20/lfecp20 24 43233432 lfec33/lfecp33 30 44344443 1. 10 i/os (1 dqs + 8 dqs + bank vref1) can function as a ddr interface in which the fpga can have a dm output but not a dqs ali gned input (in the same ddr bank as the rest of the system). package device total x8 dqs groups number of dqs groups per i/o bank 01234567 100-pin tqfp lfxp3c/lfxp3e 2 00000101 lfxp6c lfxp6e 2 00000101 144-pin tqfp lfxp3c/lfxp3e 7 10111111 lfxp6c/lfxp6e 7 10111111 208-pin pqfp lfxp3c/lfxp3e 8 11111111 lfxp6c/lfxp6e 8 11111111 256-ball fpbga lfxp3c/lfxp3e 12 22112211 lfxp6c/lfxp6e 12 22112211 lfxp10c/lfxp10e 16 22222222 lfxp15c/lfxp15e 16 22222222 lfxp20c/lfxp20e 20 33223322 388-ball fpbga lfxp10c/lfxp10e 16 22222222 lfxp15c/lfxp15e 20 33223322 lfxp20c/lfxp20e 20 33223322 484-ball fpbga lfxp15c/lfxp15e 20 33223322 lfxp20c/lfxp20e 20 33223322 672-ball fpbga lfxp20c/lfxp20e 24 44224422
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-4 figure 10-4. dq-dqs grouping figure 10-4 shows a typical dq-dqs group for both the latticeecp/ec device and the latticexp device. the ninth i/o of this group of 16 i/os (for latticeecp/ec) or 14 i/os (for latticexp) is the dedicated dqs pin. all eight pads before the dqs and seven (for latticeecp/ec) or four (for latticexp) pads after the dqs are covered by this dqs bus span. the user can assign any eight of these i/o pads to be dq data pins. hence, to implement a 32-bit wide memory interface you would need to use four such dq-dqs groups. when not interfacing with the memory, the dedicated dqs pin can be used as a general purpose i/o. each of the dedicated dqs pin is internally connected to the dqs phase shift circuitry. the pinout information contained in the latticeecp/ec and latticexp device data sheets shows pin locations for the dqs pads. table 10-2 shows an extract from the latticeecp/ec data sheet. in this case, the dqs is marked as ldqs6 (l=left side, 6 =associated pfu row/column). since dqs is always the ?th true pad in the dq-dqs group, counting from low to high pfu row/column number, ldqs6 will cover pl2a to pl9b. following this convention, there are eight pads before and seven pads after dqs for dq available following counter-clockwise for the left and bottom sides of the device, and following clockwise for the top and right sides of the device. the user can assign any eight of these pads to be dq data signals. the latticexp device follows the same method. table 10-3. ec20 pinout (from latticeecp/ec family data sheet) ball function bank lvds dual function 484 fpbga 672 fpbga pl2a 7 t vref2_7 d4 e3 pl2b 7 c vref1_7 e4 e4 pl3a 7 t c3 b1 pl3b 7 c b2 c1 pl4a 7 t e5 f3 pl4b 7 c f5 g3 pl5a 7 t d3 d2 pl5b 7 c c2 e2 pl6a 7 t ldqs6 f4 d1 pl6b 7 c g4 e1 pl7a 7 t e3 f2 pl7b 7 c d2 g2 pl8a 7 t lum0_pllt_in_a b1 f6 pl8b 7 c lum0_pllc_in_a c1 g6 pl9a 7 t lum0_pllt_fb_a f3 h4 pl9b 7 c lum0_pllc_fb_a e2 g4 pl11a 7 t g5 j4 dqs pad n* i/o pads (ninth i/o pad) dq, dm or vref1 *for latticeecp/ec: n = 16, for latticexp: n = 14.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-5 ddr software primitives this section describes the software primitives that can be used to implement ddr interfaces and provides details about how to instantiate them in the software. the primitives described include: dqsdll the dqs delay calibration dll dqsbuf the dqs delay function and the clock polarity selection logic inddrxb the ddr input and dqs to system clock transfer registers oddrxb the ddr output registers an hdl usage example for each of these primitives is listed in appendices b and c. dqsdll the dqsdll will generate a 90-degree phase shift required for the dqs signal. this primitive will implement the on-chip dqsdll. only one dqsdll should be instantiated for all the ddr implementations on one half of the device. the clock input to this dll should be at the same frequency as the ddr interface. the dll will generate the delay based on this clock frequency and the update control input to this block. the dll will update the dynamic delay control to the dqs delay block when this update control (uddcntl) input is asserted. figure 10-5 shows the primitive symbol. the active low signal on uddcntl updates the dqs phase alignment and should be initiated at the beginning of read cycles. figure 10-5. dqsdll symbol table 10-4 provides a description of the ports. table 10-4. dqsdll ports dqsdll con?uration attributes by default this dll will generate a 90-degree phase shift for the dqs strobe based on the frequency of the input reference clock to the dll. the user can control the sensitivity to jitter by using the lock_sensitivity attribute. this con?uration bit can be programmed to be either ?igh or ?ow? pl11b 7 c h6 j5 pl12a 7 t g3 k4 port name i/o de?ition clk i system clk should be at frequency of the ddr interface, from the fpga core. rst i resets the dqsdll uddcntl i provides an update signal to the dll that will update the dynamic delay. when held low this signal will update the dqsdel. lock o indicates when the dll is in phase dqsdel o the digital delay generated by the dll should be connected to the dqsbuf primitive. table 10-3. ec20 pinout (from latticeecp/ec family data sheet) ball function bank lvds dual function 484 fpbga 672 fpbga clk rst uddcntl lock dqsdel dqsdll
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-6 the dll lock detect circuit has two modes of operation controlled by the lock_sensitivity bit, which selects more or less sensitivity to jitter. if this dll is operated at or above 150 mhz, it is recommended that the lock_sensitivity bit be programmed ?igh (more sensitive). for operation running at or under 100 mhz it is recommended that the bit be programmed ?ow (more tolerant). for 133 mhz, the lock_sensitivity bit can go either way. dqsbuf this primitive implements the dqs delay and the dqs transition detector logic. figure 10-6 shows the dqsbufb function. the preamble detect signal is also generated within this primitive. figure 10-6. dqsbufb function figure 10-7 shows the primitive symbol and its ports. dqsi is the dqs signal from the memory. prmbdet is the preamble detect signal that is generated from the dqsi input. read and clk are user interface signals coming from the fpga logic. the dqsdll block sends digital control line dqsdel to this block. the dqs is delayed based on this input from the dqsdll. dqso is the delayed dqs and is connected to the clock input of the ?st set of ddr registers. figure 10-7. dqsbufb symbol table 10-5 provides a description of the i/o ports associated with the dqsbufb primitive. dqsdel dqs transition detect prmbdet dqsi dqso + - + - v ref - dv (dv ~ 170mv) read clk dqsbufb dqsdel v ref ddrclkpol dqsc prmbdet dqsi dqsbufb clk read dqso ddrclkpol dqsc prmbdet dqsdel
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-7 table 10-5. dqsbufb ports notes: 1. the ddr clock polarity output from this block should be connected to the ddclkpol inputs of the input register blocks (iddrxb). read pulse generation the read signal to the dqsbufb block is internally generated in the fpga core. the read signal will go high when the read command to control the ddr sdram is initially asserted. this should normally precede the dqs preamble by one cycle yet may overlap the trailing bits of a prior read cycle. the dqs detect circuitry of the latti- ceecp/ec and latticexp devices require the falling edge of the read signal to be placed within the preamble stage. the preamble state of the dqs can be detected using the cas latency and the round trip delay for the signals between the fpga and the memory device. note that the internal fpga core generates the read pulse. the rise of the read pulse needs to coincide with the initial read command of the read burst and needs to go low before the preamble goes high. figure 10-8 shows the read pulse timing example with respect to the prmbdet signal. figure 10-8. read pulse generation port name i/o de?ition dqsi i dqs strobe signal from memory clk i system clk read i read generated from the fpga core dqsdel i dqs delay from the dqsdll primitive dqso o delayed dqs strobe signal, to the input capture register block dqsc o dqs strobe signal before delay, going to the fpga core logic ddrclkpol o ddr clock polarity signal prmbdet o preamble detect signal, going to the fpga core logic read dqs prmbdet first dqs tra n sitio n preamble prior read cycle postamble postamble ok read fail read fail v th read ok
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-8 iddrxb this primitive will implement the input register block. the software defaults to ce enabled unless otherwise speci- ?d. the eclk input is used to connect to the dqs strobe coming from the dqs delay block (dqsbufb primitive). the sclk input should be connected to the system (fpga) clock. the sclk and ce inputs to this primitive will be used primarily to synchronize the ddr inputs. ddrclkpol is an input from the dqs clock polarity tree. this sig- nal is generated by the dqs transition detect circuit in the hardware. figure 10-9 shows the primitive symbol and the i/o ports. figure 10-9. iddrxb symbol table 10-6 provides a description of all i/o ports associated with the iddrxb primitive. table 10-6. iddrxb ports note: 1. the ddrclkpol input to iddrxb should be connected to the ddrclkpol output of dqsbufb. oddrxb the oddrxb primitive implements both the write and the tristate functions. this primitive is used to output ddr data and the dqs strobe to the memory. the ckp and ckn can also be generated using this primitive. all the ddr output tristate implementations are also implemented using the same primitive. figure 10-10 shows the oddrxb primitive symbol and its i/o ports. port name i/o de?ition d i ddr data eclk i the phase shifted dqs should be connected to this input lsr i reset sclk i system clk ce i clock enable ddrclkpol i ddr clock polarity signal qa o data at the positive edge of the clk qb o data at the negative edge of the clk iddrxb eclk lsr qa qb d sclk ce ddrclkpol
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-9 figure 10-10. oddrxb symbol table 10-7 provides a description of all i/o ports associated with the oddrxb primitive. table 10-7. oddrxb ports notes : 1. lsr should be held low during ddr write operation. by default, the software will be implemented ce high and lsr low. 2. ddr output and tristate registers do not have ce support. lsr is available for the tristate ddrx mode (while reading). the lsr will default to set when used in the tristate mode. 3. ce and lsr support is available for the regular (non-ddr) output mode. 4. when asserting reset during ddr writes, it is important to keep in mind that this would only reset the ffs and not the latches. memory read implementation the latticeecp/ec and latticexp devices contain a variety of features to simplify implementation of the read por- tion of a ddr interface: dll compensated dqs delay elements ddr input registers automatic dqs to system clock domain transfer circuitry the latticeecp/ec and latticexp device data sheets detail these circuit elements. three primitives in the lattice isplever design tools represent the capability of these three elements. the dqs- dll represents the dll used for calibration. the iddrxb primitive represents the ddr input registers and clock domain transfer registers. finally, the dqsbufb represents the dqs delay block and the clock polarity control logic. these primitives are explained in more detail in the following sections of this document. figure 10-11 illus- trates how to hook these primitives together to implement the read portion of a ddr memory interface. the ddr software primitives section describes each of the primitives and its instantiation in more detail. appendices a and b provide example code to implement the complete i/o section of a memory interface within a latticeecp/ec or lat- ticexp device. port name i/o de?ition clk i system clk da i data at the positive edge of the clock db i data at the negative edge of the clock lsr i reset q i ddr data to the memory q oddrxb clk da db lsr
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-10 figure 10-11. software primitive implementation for memory read read timing waveforms figure 10-12 and figure 10-13 show read data transfer for two cases based on the results of the dqs transition detector logic. this circuitry decides whether or not to invert the phase of fpga system clk to the synchronization registers based on the relative phases of prmbdet and clk. case 1 ?if clk = 0 on the 1st prmbdet transition, then ddrclkpol = 0, hence no inversion required. (figure 10-12) case 2 ?if clk=1 on the 1st prmbdet then ddrclkpol = 1, the system clock (clk) needs to be inverted before it is used for synchronization. (figure 10-13) the signals a, b and c illustrate the read cycle half clock transfer at different stages of iddrx registers. the ?st stage of the register captures data on the positive edge as shown by signal a and negative edge as shown by sig- nal b. the data stream a goes through an additional half clock cycle transfers shown by signal c. phase aligned data streams b and c are presented to the next stage registers clocked by the fpga clk 6 ddrclkpol dqs reset clk uddcntl lock dqsdll dqsi clk read dqsdel read dq dqso sclk eclk ddrclkpol d lsr ce qa qb rst uddcntl dqsdel datain_p datain_n dqsc prmbdet lock dqsbufb iddrxb ce dqsc prmbdet
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-11 figure 10-12. read data transfer when ddrclkpol=0 dqs at pin dq at pin dqs at iol fpga clk ddrclkpol= 0 prmbdet clk to sync io registers a b c p0 n0 n1 p1 p0 n0 p1 n1 p0 p1 n0 n1 p0 p1 p0 n0 datain_p datain_n dq at iol notes - (1) ddr memory sends dq aligned to dqs strobe. (2) the dqs strobe is delayed by 90 degree using the dedicated dqs logic. (3) dq is now center aligned to dqs strobe. (4) prmbdet is the preamble detect signal generated using the dqsbufb primitive. this is used to generate the ddrclkpol signal. (5) the first set of io registers a and b, capture data on the positive edge and negative edge of dqs. (6) io register c transfers data so that both data are now aligned to negative edge of dqs. (7) ddclkpol signal generated will determine if the clk going into the synchronization registers need to be inverted. in this case, the ddrclkpol=0 as the clk is low at the 1 st rising edge of prmbdet. (8) the io synchronization registers capture data at on positive edge of the fpga clk.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-12 figure 10-13. read data transfer when ddrclkpol=1 data read critical path data in the second stage ddr registers can be registered either on the positive edge or on the falling edge of fpga clock depending on the ddrclkpol signal. in order to ensure that the data transferred to the fpga core registers is aligned to the rising edge of system clk, this path should be constrained with a half clock transfer. this half clock transfer can be forced in the software by assigning a multicycle constraint (multicycle of 0.5 x) on all the data paths to the ?st pfu register. dqs at pin dq at pin dqs at iol prmbdet a b c p0 n0 n1 p1 p0 n0 p1 n1 p0 p1 n0 n1 p0 p1 dq at iol fpga clk ddrclkpol=1 p0 n0 clk to sync io registers datain_p datain_n notes - (1) ddr memory sends dq aligned to dqs strobe. (2) the dqs strobe is delayed by 90 degree using the dedicated dqs logic. (3) dq is now center aligned to dqs strobe. (4) prmbdet is the preamble detect signal generated using the dqsbufb primitive. this is used to generate the ddrclkpol signal. (5) the first set of io registers a and b, capture data on the positive edge and negative edge of dqs. (6) io register c transfers data so that both data are now aligned to negative edge of dqs. (7) ddclkpol signal generated will determine if the clk going into the synchronization registers need to be inverted. in this case, the ddrclkpol=1 as the clk is high at the 1 st rising edge of prmbdet. (8) the io synchronization registers capture data at on negative edge of the fpga clk.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-13 dqs postamble at the end of a read cycle, the ddr sdram device executes the read cycle postamble and then immediately tristates both the dq and dqs output drivers. since neither the memory controller (fpga) nor the ddr sdram device are driving dq or dqs at that time, these signals ?at to a level determined by the off-chip termination resistors. while these signals are ?ating, noise on the dqs strobe may be interpreted as a valid strobe signal by the fpga input buffer. this can cause the last read data captured in the iol input ddr registers to be overwrit- ten before the data has been transferred to the free running resynchronization registers inside the fpga. figure 10-14. postamble effect on read latticeecp/ec and latticexp devices have extra dedicated logic in the in the dqs delay block that will prevent this postamble problem. the dqs postamble logic is automatically implemented when the user instantiates the dqs delay logic (dqsbufb software primitive) in a design. this postamble solution was implemented in all the devices of the latticeecp/ec and latticexp families except the lfec20/lfecp20 device. for this device, it is recommended that the user issue an extra read command to assure correct data has been transferred to the synchronization registers. the circumstances under which the extended read cycle is issued are given in table 10-8. table 10-8. ddr read postamble current command next command action lost cycles read (row x, bank y) read (row x, bank y) none. none read (any address) nop extend the current read command. 1 3 read (row x, bank y) read (row n, bank y) extend the current read to (row x, bank y) consecutive to current command 3 read (row x, bank y) read (row x, bank n) if the row x, bank n was open, do nothing. else, extend the current read to row x, bank y 3 read (any address) write/lmr extend the current read command. 3 1. current read is extended one or more additional clock cycles. p0 p1 n0 p0 dq at iol dqs at pin dq at pin dqs at iol p0 n0 n1 p1 n1 p0 n0 n1 p1 p1 clk at synce reg datain_p datain_n a b c p0 n0
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-14 figure 10-15. postamble solution with extra read command memory write implementation to implement the write portion of a ddr memory interface, two streams of single data rate data must be multi- plexed together with data transitioning on both edges of the clock. in addition, during a write cycle, dqs must arrive at the memory pins center-aligned with data, dq. along with the strobe and data this portion of the interface pro- vides the clkp, clkn address/command and data mask (dm) signals to the memory. latticeecp/ec and latticexp devices contain ddr output and tri-state registers along with plls that allow the easy implementation of the write portion of the ddr memory interfaces. the ddr output registers can be accessed in the design tools via the oddrxb primitive. all ddr output signals (?ddr, cmd? dqs, dq, dm) are initially aligned to the rising edge of clk inside the fpga core. these signals are used for the entire ddr write interface or the controls of ddr read interface. the relative phase of the signals may be adjusted in the iol logic before departing the fpga. the adjustments are shown in figure 16 the adjustments are as follows: the pll is used to generate a 90 degree phase shifted clock. this 90 degree phase shifted clock will be used to generate dqs and the differential clocks going to the memory. the clkp needs to be centered relative to the addr,cmd signal, which is an sdr signal. this is accomplished by inverting the clkp signal relative to the plls 90 degree phase shifted clk. the ddr clock can be generated by assigning ? to the da input and ? to the db inputs of the oddrxb primi- tive as shown in figure 10-16. this is then fed into a sstl25 differential output buffer to generate clkp and clkn differential clocks. generating the clkn in this manner would prevent any skew between the two signals. the ddr interface speci?ation for t dss and t dsh parameters, de?ed as dqs falling to clkp rising setup and hold times must be met. this is met by making clkp and dqs identical in phase. dqs is inverted to match clkp (= clk + 270). this is accomplished by routing the positive dqs data in core logic to db, and negative dqs data in core logic to da inputs of the oddrxb primitive. p0 p1 dq at iol dqs at pin dq at pin dqs at iol p0 n0 n1 p1 p0 n0 n1 p1 clk at synce reg a b c n0 n1 p0 p1 datain_p datain_n p0 n0 p1 n1
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-15 internally the dqs and addr/cmd signals are clocked using the primary fpga clock. therefore, the user will need to do a 1/4 (one-quarter) clock transfer from the core logic to the ddr registers. timing can be hard to meet, so it is recommended that the user ?st register these signals with the inverted clock, so that the transfer from the core logic to i/o registers will only require a 1/2 (half) clock transfer. the data dq and dm needs to be delayed by 90?as it leaves the fpga. this is to center the data and data mask relative to the dqs when it reaches the ddr memory. this can be accomplished by inverting the clk to the dq and dm data. the dm signal is generated using the same clock as the dq data pin. the memory masks the dq signals if the dm pins are driven high. the tristate control for the data output can also be implemented using the oddrxb primitive. figure 10-16 illustrates how to hook up the oddrxb primitives and the pll. the ddr software primitives section describes each of the primitives and its instantiation in more detail. appendix a and appendix b provide example code for implementing the complete i/o section of a memory interface for a latticeecp/ec or latticexp device. figure 10-16. software primitive implementation for memory write pll clk dqs dq core logic clk clkn clk + 90 pio logic ddr memory device dataout_p dataout_n clkp ? dm oddrxb clk da db q q lsr q oddrxb clk da db q lsr oddrxb clk da db q lsr oddrxb clk da db q lsr oddrxb clk da db q lsr oddrxb clk da db q lsr ? datatri_p datatri_n dqstri_p dqstri_n (from user logic) (from user logic) addr/ cmd d ? ? d q d q d q d q d q
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-16 write timing waveforms figure 10-17 shows ddr write side data transfer timing for the dq data pad and the dqs strobe pad. when writ- ing to the ddr memory device, the dm (data mask) and the addr/ cmd (address and command) signals are also sent to the memory device along with the data and strobe signals. figure 10-17. ddr write data transfer for dq data design rules/guidelines listed below are some rules and guidelines to keep in mind when implementing ddr memory interfaces in the lat- ticeecp/ec and latticexp devices. the latticeecp/ec and latticexp devices have dedicated dq-dqs banks. please refer to the logical sig- nal connections of the groups in the latticeecp/ec and latticexp data sheets before locking these pins. there are two dqsdlls on the device, one for the top half and one for the bottom half. hence, only one dqsdll primitive should be instantiated for each half of the device. since there is only one dqsdll on each half of the device, all the ddr memory interfaces on that half of the device should run at the same fre- quency. each dqsdll will generate 90 degree digital delay bits for all the dqs delay blocks on that half of the device based on the reference clock input to the dll. notes - (1) dataout_p and dataout_n are inputs to the ddr output registers. (2) dqs is generated at 270 degree phase of clk. (3) clkp is generated simular to dqs and clkn is the inverted clkp. (4) dq is generated at 180 degree phase of clk. (5) dq is center aligned with the dqs strobe signal when it reaches the memory. dataout_n dataout_p p0 p1 p2 n0 n1 n2 clk dqs p0 n0 n1 p2 n2 p1 clk +270 clk +180 clkp clkn dq
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-17 the ddr sdram interface supports the sstl25 i/o standard, therefore the interface pins should be assigned as sstl25 i/o type. when implementing a ddr interface, the vref1 of the bank is used to provide the reference voltage for the interface pins. appendix f shows ddr400 implementation results of the latticeec advanced evaluation board. qdr ii interface qdr ii sram is a new memory technology de?ed by a number of leading memory vendors for high-performance and high-bandwidth communication applications. qdr is a synchronous pipelined burst sram with two separate unidirectional data buses dedicated for read and write operations running at double data rate. both the qdr ii read and write interfaces use hstl 1.8v i/o standard. a qdr ii memory controller can be easily implemented using the latticeecp/ec and latticexp devices by taking advantage of the ddr i/o registers. for latticeecp/ec and latticexp devices, oddrxb primitives are used on the qdr outputs and pfu registers are used on the qdr inputs to implement the ddr interface. to see the details of this implementation refer to lattice reference design rd1019, qdr memory controller on the lattice web site at www .latticesemi.com . fcram (fast cycle random access memory) interface fcram is a ddr-type dram, which performs data output at both the rising and the falling edges of the clock. fcram devices operate at a core voltage of 2.5v with sstl class ii i/o. it has enhanced both the core and peripheral logic of the sdram. in fcram the address and command signals are synchronized with the clock input, and the data pins are synchronized with the dqs signal. data output takes place at both the rising and falling edges of the dqs. dqs is in phase with the clock input of the device. the ddr sdram and ddr fcram control- ler will have different pin outs. latticeecp/ec and latticexp devices can implement an fcram interface using the dedicated dqs logic, input ddr registers and output ddr registers as described in the implementing memory interfaces section of this docu- ment. generation of address and control signals for fcram are different compared to the ddr sdram devices. please refer to the fcram data sheets to see detailed speci?ations. toshiba, inc. and fujitsu, inc. offer fcram devices in 256mb densities. they are available in x8 or x16 con?urations. generic high speed ddr implementation in addition to the ddr memory interface, users can use the i/o logic registers to implement a high speed ddr interface. ddr data write operations can be implemented using the ddr output registers similar to the memory interface implementation using the oddrxb primitives. on the input side, the read interface can be implemented using the core logic pfu registers. the pfu register next to the i/o cells can be used to de-mux the ddr data to single data rate data. this method of implementing ddr can run at 300 mhz when accompanied by proper preferences in the software. the hdl and the preferences to implement this ddr interface are listed in appendix d of this document. board design guidelines the most common challenge associated with implementing ddr memory interfaces is the board design and lay- out. users must strictly follow the guidelines recommended by memory device vendors. some common recommendations include matching trace lengths of interface signals to avoid skew, proper dq- dqs signal grouping, proper termination of the sstl2 i/o standard, proper vref and vtt generation decoupling and proper pcb routing.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-18 some reference documents that discuss board layout guidelines: www .idt.com , idt, pcb design for double data rate memory. www .motorola.com , an2582, hardware and layout design considerations for ddr interfaces. www .micron.com , tn4607, ddr 333 design guide for two dimm systems references www .jedec.org ?jedec standard 79, double data rate (ddr) sdram speci?ation www .micron.com ?ddr sdram data sheets www .in nion.com ?ddr sdram data sheets www .samsung.com ?ddr sdram data sheets www .latticesemi.com ?rd1019 qdr memory controller reference design for latticeecp/ec devices www .toshiba.com ?ddr fcram data sheet www .fujitsu.com ?ddr fcram data sheet www .latticesemi.com ?latticeec advanced evaluation board users guide www .latticesemi.com ?ddr sdram controller (pipelined version for latticeecp/ec devices) user's guide technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history date version change summary previous lattice releases. february 2007 03.2 updated generic high speed ddr implementation section. updated appendix d.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-19 appendix a. using ipexpress to generate ddr modules the input and output ddr module can be generated using ipexpress. the i/o section under the architecture mod- ules provides two options to the user: 1. ddr_generic ?the option allows generation of a generic ddr interface, which in the case of latti- ceecp/ec and latticexp devices, is only the output side ddr. the input side for a generic ddr interface must be implemented using pfu registers. appendix d provides the example code for the input side generic ddr. 2. ddr_mem ?this option allows the user to generate a complete ddr memory interface. it will generate both the read and write side interface required to interface with the memory. ipexpress generates only the modules that are implemented within the iologic. any logic required in the fpga core to complete the memory interface must be implemented by the user. figure 10-18. ipexpress i/o section ddr generic ddr generic will generate the output ddr (oddrxb) primitives for a given bus width. the user has the option to enable or disable tristate control to the output ddr registers. figure 10-19 shows the ddr generic views of ipex- press.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-20 figure 10-19. ddr generic con?uration options ddr memory interface this ipexpress option generates both read and write interfaces using all ddr primitives for a given bus width. figure 10-20 shows the options under this section. figure 10-20. con?uration options for ddr memory interface
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-21 appendix b. verilog example for ddr input and output modules module ddr_mem (dq, dqs, clk, reset, uddcntl, read, datain_p, datain_n, dqsc, prmbdet, lock, ddrclkpol, clk90, dqstri_p, dqstri_n, datatri_p, datatri_n, dataout_p, dataout_n, ddrclk); inout [7:0] dq/* synthesis io_type="sstl25_ii"*/; inout dqs/* synthesis io_type="sstl25_ii"*/; --clk is the core clock and clk90 is the 90 degree phase shifted clock coming from the pll input clk, clk90; input reset, uddcntl, read; input [7:0] dataout_p, dataout_n; input [7:0] datatri_p, datatri_n; input dqstri_p, dqstri_n; output [7:0] datain_p; output[7:0] datain_n; output dqsc, prmbdet, lock, ddrclkpol; output ddrclk /* synthesis io_type="sstl25d_ii"*/ ; wire vcc_net,gnd_net; wire dqsbuf, dqsdel, clk, ddrclkpol_sig; wire [7:0] ddrin, ddrout, tridata; wire dqsout, tridqs, dqsin, ddrclk; assign vcc_net = 1'b1; assign gnd_net = 1'b0; assign ddrclkpol = ddrclkpol_sig; //-------bidirectional buffers ------------------------------------------------------ bb bidiinst0 (.i(ddrout[0]), .t(tridata[0]), .o(ddrin[0]), .b(dq[0])); bb bidiinst1 (.i(ddrout[1]), .t(tridata[1]), .o(ddrin[1]), .b(dq[1])); bb bidiinst2 (.i(ddrout[2]), .t(tridata[2]), .o(ddrin[2]), .b(dq[2])); bb bidiinst3 (.i(ddrout[3]), .t(tridata[3]), .o(ddrin[3]), .b(dq[3])); bb bidiinst4 (.i(ddrout[4]), .t(tridata[4]), .o(ddrin[4]), .b(dq[4])); bb bidiinst5 (.i(ddrout[5]), .t(tridata[5]), .o(ddrin[5]), .b(dq[5])); bb bidiinst6 (.i(ddrout[6]), .t(tridata[6]), .o(ddrin[6]), .b(dq[6])); bb bidiinst7 (.i(ddrout[7]), .t(tridata[7]), .o(ddrin[7]), .b(dq[7])); //bidirectional strobe, dqs bb bidiinst8(.i(dqsout), .t(tridqs), .o(dqsin), .b(dqs)); //------------------------------------------------------------------------------------ //-----------ddr input --------------------------------------------------------------- dqsbufb u8 (.dqsi(dqsin), .clk(clk), .read(read), .dqsdel(dqsdel), .ddrclkpol(ddrclkpol_sig), .dqsc(dqsc), .prmbdet(prmbdet), .dqso(dqsbuf)); dqsdll u9 (.clk(clk), .uddcntl(uddcntl), .rst(reset), .dqsdel(dqsdel), .lock(lock)); iddrxb ul0 (.d(ddrin[0]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[0]), .qb(datain_n[0])); iddrxb ul1 (.d(ddrin[1]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[1]), .qb(datain_n[1]));
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-22 iddrxb ul2 (.d(ddrin[2]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[2]), .qb(datain_n[2])); iddrxb ul3 (.d(ddrin[3]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[3]), .qb(datain_n[3])); iddrxb ul4 (.d(ddrin[4]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[4]), .qb(datain_n[4])); iddrxb ul5 (.d(ddrin[5]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[5]), .qb(datain_n[5])); iddrxb ul6 (.d(ddrin[6]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[6]), .qb(datain_n[6])); iddrxb ul7 (.d(ddrin[7]), .eclk(dqsbuf), .sclk(clk), .ce(vcc_net), .ddrclkpol(ddrclkpol_sig), .lsr(reset), .qa(datain_p[7]), .qb(datain_n[7])); //---------------------------------------------------------------------------------------- //----tristate instantiations------------------------------------------------------------- // ddr trisate for data, dq oddrxb t0 (.da(datatri_p[0]), .db(datatri_n[0]), .lsr(reset), .clk(~clk), .q(tridata[0])); oddrxb t1 (.da(datatri_p[1]), .db(datatri_n[1]), .lsr(reset), .clk(~clk), .q(tridata[1])); oddrxb t2 (.da(datatri_p[2]), .db(datatri_n[2]), .lsr(reset), .clk(~clk), .q(tridata[2])); oddrxb t3 (.da(datatri_p[3]), .db(datatri_n[3]), .lsr(reset), .clk(~clk), .q(tridata[3])); oddrxb t4 (.da(datatri_p[4]), .db(datatri_n[4]), .lsr(reset), .clk(~clk), .q(tridata[4])); oddrxb t5 (.da(datatri_p[5]), .db(datatri_n[5]), .lsr(reset), .clk(~clk), .q(tridata[5])); oddrxb t6 (.da(datatri_p[6]), .db(datatri_n[6]), .lsr(reset), .clk(~clk), .q(tridata[6])); oddrxb t7 (.da(datatri_p[7]), .db(datatri_n[7]), .lsr(reset), .clk(~clk), .q(tridata[7])); // ddr trisate for strobe, dqs oddrxb t8 (.da(dqstri_p), .db(dqstri_n), .lsr(reset), .clk(clk90), .q(tridqs)); //------------------------------------------------------------------------------------------ //-----------dq output---------------------------------------------------------------------- oddrxb o0 (.da(dataout_p[0]), .db(dataout_n[0]), .lsr(reset), .clk(~clk), .q(ddrout[0])); oddrxb o1 (.da(dataout_p[1]), .db(dataout_n[1]), .lsr(reset), .clk(~clk), .q(ddrout[1])); oddrxb o2 (.da(dataout_p[2]), .db(dataout_n[2]), .lsr(reset), .clk(~clk), .q(ddrout[2])); oddrxb o3 (.da(dataout_p[3]), .db(dataout_n[3]), .lsr(reset), .clk(~clk), .q(ddrout[3])); oddrxb o4 (.da(dataout_p[4]), .db(dataout_n[4]), .lsr(reset), .clk(~clk), .q(ddrout[4])); oddrxb o5 (.da(dataout_p[5]), .db(dataout_n[5]), .lsr(reset), .clk(~clk), .q(ddrout[5])); oddrxb o6 (.da(dataout_p[6]), .db(dataout_n[6]), .lsr(reset), .clk(~clk), .q(ddrout[6])); oddrxb o7 (.da(dataout_p[7]), .db(dataout_n[7]), .lsr(reset), .clk(~clk), .q(ddrout[7])); //------------------------------------------------------------------------------------------- //--------------- dqs output----------------------------------------------------------------- oddrxb o8 (.da(gnd_net), .db(vcc_net), .lsr(reset), .clk(clk90), .q(dqsout)); //------------------------------------------------------------------------------------------- //--------------- clkoutp and clkoutn generation--------------------------------------------- oddrxb o9 (.da(gnd_net), .db(vcc_net), .lsr(reset), .clk(clk90), .q(ddrclk)); //------------------------------------------------------------------------------------------- endmodule
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-23 appendix c. vhdl example for ddr input and output modules library ieee; use ieee.std_logic_1164.all; library ec; use ec.components.all; entity ddr_mem is port( dq : inout std_logic_vector(7 downto 0 ); dqs : inout std_logic; clk : in std_logic; -- core clock clk90 : in std_logic; -- 90 degree phase shifted clock from the pll reset : in std_logic; uddcntl : in std_logic; read : in std_logic; dataout_p : in std_logic_vector(7 downto 0); dataout_n : in std_logic_vector(7 downto 0); datatri_p : in std_logic_vector(7 downto 0); datatri_n : in std_logic_vector(7 downto 0); dqstri_p : in std_logic; dqstri_n : in std_logic; ddrclk : out std_logic; datain_p : out std_logic_vector(7 downto 0); datain_n : out std_logic_vector(7 downto 0); dqsc : out std_logic; prmbdet : out std_logic; lock : out std_logic; ddrclkpol : out std_logic); --*****ddr interface signals assigned sstl25 io standard ************* attribute io_type : string; attribute io_type of ddrclk : signal is "sstl25d_ii"; attribute io_type of dq : signal is "sstl25_ii"; attribute io_type of dqs : signal is "sstl25_ii"; end ddr_mem; architecture structure of ddr_mem is --*****ddr input register********************************************* component iddrxb port( d : in std_logic; eclk : in std_logic; sclk : in std_logic; ce : in std_logic; lsr : in std_logic; ddrclkpol : in std_logic; qa : out std_logic; qb : out std_logic); end component;
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-24 --*******ddr output register ******************************************* component oddrxb port( clk : in std_logic; da : in std_logic; db : in std_logic; lsr : in std_logic; q : out std_logic); end component; --*******bidirectional buffer******************************************** component bb port( i : in std_logic; t : in std_logic; o : out std_logic; b : inout std_logic); end component; --******dqs dll component************************************************* component dqsdll port( clk : in std_logic; rst : in std_logic; uddcntl : in std_logic; lock : out std_logic; dqsdel : out std_logic); end component; --****** dqs delay block*************************************************** component dqsbufb port( dqsi : in std_logic; clk : in std_logic; read : in std_logic; dqsdel : in std_logic; dqso : out std_logic; ddrclkpol : out std_logic; dqsc : out std_logic; prmbdet : out std_logic); end component; signal dqsbuf : std_logic; signal dqsdel : std_logic; signal ddrclkpol_sig : std_logic; signal ddrin : std_logic_vector(7 downto 0 ); signal ddrout : std_logic_vector(7 downto 0 ); signal tridata : std_logic_vector(7 downto 0 ); signal dqsout : std_logic; signal tridqs : std_logic; signal dqsin : std_logic; signal vcc_net : std_logic; signal gnd_net : std_logic;
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-25 signal clkinv : std_logic; signal ddrclk : std_logic; begin vcc_net <= '1'; gnd_net <= '0'; clkinv<= not clk; ddrclkpol<=ddrclkpol_sig; --*************bidirectional buffers***************************************************** bidiinst0 : bb port map( i => ddrout(0),t => tridata(0),o => ddrin(0),b => dq(0)); bidiinst1 : bb port map( i => ddrout(1),t => tridata(1),o => ddrin(1),b => dq(1)); bidiinst2 : bb port map( i => ddrout(2),t => tridata(2),o => ddrin(2),b => dq(2)); bidiinst3 : bb port map( i => ddrout(3),t => tridata(3),o => ddrin(3),b => dq(3)); bidiinst4 : bb port map( i => ddrout(4),t => tridata(4),o => ddrin(4),b => dq(4)); bidiinst5 : bb port map( i => ddrout(5),t => tridata(5),o => ddrin(5),b => dq(5)); bidiinst6 : bb port map( i => ddrout(6),t => tridata(6),o => ddrin(6),b => dq(6)); bidiinst7 : bb port map( i => ddrout(7),t => tridata(7),o => ddrin(7),b => dq(7)); bidiinst8 : bb port map( i=> dqsout, t=> tridqs, o=> dqsin, b=> dqs); --*************************************************************************************** --*************ddrinput****************************************************************** --dqsdll, generates the dqs delay i0: dqsdll port map(clk=>clk, uddcntl=> uddcntl, rst=> reset, dqsdel=> dqsdel, lock => lock); i1: dqsbufb port map( dqsi=> dqsin, clk=>clk, read=> read, dqsdel=> dqsdel, ddrclkpol=> ddrclkpol_sig, dqsc=> dqsc, prmbdet=> prmbdet, dqso=> dqsbuf); --ddr input primitives i2 : iddrxb port map(d=> ddrin(0), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(0), qb => datain_n(0)); i3 : iddrxb port map(d=> ddrin(1), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(1), qb => datain_n(1)); i4 : iddrxb port map(d=> ddrin(2), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(2), qb => datain_n(2)); i5 : iddrxb port map(d=> ddrin(3), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(3), qb => datain_n(3)); i6 : iddrxb port map(d=> ddrin(4), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(4), qb => datain_n(4)); i7 : iddrxb port map(d=> ddrin(5), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(5), qb => datain_n(5));
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-26 i8 : iddrxb port map(d=> ddrin(6), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(6), qb => datain_n(6)); i9 : iddrxb port map(d=> ddrin(7), eclk=> dqsbuf, sclk => clk, ce => vcc_net, ddrclkpol=> ddrclkpol_sig, lsr => reset, qa =>datain_p(7), qb => datain_n(7)); --*************************************************************************************** --*****tristate instantiations*********************************************************** -- ddr trisate for data, dq t0 : oddrxb port map( da => datatri_p(0), db => datatri_n(0), lsr => reset, clk => clkinv, q => tridata(0)); t1 : oddrxb port map( da => datatri_p(1), db => datatri_n(1), lsr => reset, clk => clkinv, q => tridata(1)); t2 : oddrxb port map( da=> datatri_p(2), db => datatri_n(2), lsr => reset, clk => clkinv, q => tridata(2)); t3 : oddrxb port map( da => datatri_p(3), db => datatri_n(3), lsr => reset, clk => clkinv, q => tridata(3)); t4 : oddrxb port map( da => datatri_p(4), db => datatri_n(4), lsr => reset, clk => clkinv, q => tridata(4)); t5 : oddrxb port map( da => datatri_p(5), db => datatri_n(5), lsr => reset, clk => clkinv, q => tridata(5)); t6 : oddrxb port map( da => datatri_p(6), db => datatri_n(6), lsr => reset, clk => clkinv, q => tridata(6)); t7 : oddrxb port map( da => datatri_p(7), db => datatri_n(7), lsr => reset, clk => clkinv, q => tridata(7)); --ddr trisate for strobe, dqs t8: oddrxb port map( da =>dqstri_p, db=> dqstri_n, lsr=> reset, clk=> clk90, q => tridqs); --**************************************************************************************** --***************ddr output*************************************************************** --dq output o0 : oddrxb port map( da => dataout_p(0), db => dataout_n(0), lsr => reset, clk => clkinv, q => ddrout(0)); o1 : oddrxb port map( da => dataout_p(1), db => dataout_n(1), lsr => reset, clk => clkinv, q => ddrout(1)); o2 : oddrxb port map( da => dataout_p(2), db => dataout_n(2), lsr => reset, clk => clkinv, q => ddrout(2)); o3 : oddrxb port map( da => dataout_p(3), db => dataout_n(3), lsr => reset, clk => clkinv, q => ddrout(3)); o4 : oddrxb port map( da => dataout_p(4), db => dataout_n(4), lsr => reset, clk => clkinv, q => ddrout(4)); o5 : oddrxb port map( da => dataout_p(5), db => dataout_n(5), lsr => reset, clk => clkinv, q => ddrout(5)); o6 : oddrxb port map( da => dataout_p(6), db => dataout_n(6), lsr => reset, clk => clkinv, q => ddrout(6)); o7 : oddrxb port map( da => dataout_p(7), db => dataout_n(7), lsr => reset, clk => clkinv, q => ddrout(7));
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-27 --dqs output o8: oddrxb port map( da => gnd_net, db => vcc_net, lsr => reset, clk => clk90, q => dqsout); --clkp and clkn generation o9 : oddrxb port map( da => vcc_net, db => gnd_net, lsr => reset, clk => clk90, q => ddrclk); --****************************************************************************************** end structure;
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-28 appendix d. generic (non-memory) high-speed ddr interface the following hdl implements the ddr input interface using pfu registers for non-memory ddr applications. vhdl implementation library ieee; use ieee.std_logic_1164.all; library ec; use ec.components.all; entity ddrin is port (rst : in std_logic; ddrclk: in std_logic; ddrdata: in std_logic_vector(7 downto 0); datap: out std_logic_vector(7 downto 0); datan: out std_logic_vector(7 downto 0)); end ddrin; architecture structure of ddrin is -- parameterized module component declaration component pll90 port (clk: in std_logic; reset: in std_logic; clkop: out std_logic; clkos: out std_logic; lock: out std_logic); end component; signal pos0 : std_logic_vector( 7 downto 0 ); signal pos1 : std_logic_vector( 7 downto 0 ); signal neg0 : std_logic_vector( 7 downto 0 ); signal clklock : std_logic; signal ddrclk0: std_logic; signal ddrclk90: std_logic; signal vcc_net : std_logic; signal gnd_net: std_logic; attribute syn_useioff : boolean; attribute syn_useioff of structure : architecture is false; begin vcc_net <= '1'; gnd_net <= '0'; -- parameterized module component instance i0 : pll90 port map (clk=>ddrclk, reset=>rst, clkop=>ddrclk0, clkos=>ddrclk90, lock=>clklock); demux: process (rst, ddrclk90) begin if rst = '1' then pos0 <= (others => '0'); neg0 <= (others => '0'); pos1 <= (others => '0'); elsif rising_edge(ddrclk90) then pos0 <= ddrdata; elsif falling_edge(ddrclk90) then
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-29 neg0 <=ddrdata; pos1 <=pos0; end if; end process demux; synch: process (rst, ddrclk90) begin if rst = '1' then datap <= (others => '0'); datan <= (others => '0'); elsif rising_edge(ddrclk90) then datap<= pos1; elsif falling_edge(ddrclk90) then datan<= neg0; end if; end process synch; end structure;
verilog example module ddrin (rst, ddrclk, ddrdata, datap, datan)/*synthesis syn_useioff = 0*/; // inputs input rst; input ddrclk; input [7:0] ddrdata; // outputs output [7:0] datap, datan; reg [7:0] pos0/*synthesis syn_keep=1*/; reg [7:0] pos1/*synthesis syn_keep=1*/; reg [7:0] neg0/*synthesis syn_keep=1*/; reg [7:0] datap, datan/*synthesis syn_keep=1*/; //pll signals wire ddrclk0; wire ddrclk90; pll i0 (.clk(ddrclk), .reset(rst), .clkop(ddrclk0), .clkos(ddrclk90), .lock(clklock)); always @ ( posedge ddrclk90) begin if (rst) begin pos0 <= 0; end else begin pos0 <= ddrdata; end end always@ (negedge ddrclk90) begin if (rst) begin neg0<=0; pos1<=0; end else begin neg0<=ddrdata; pos1<=pos0; end end always @ (posedge ddrclk90) begin if (rst) begin datap<= 0; datan<= 0; end else begin datap<= pos1; datan<= neg0; end
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-31 end endmodule preference file in order to run the above ddr pfu implementation at 300mhz, the following preferences were added to the soft- ware preference ?e. commercial; frequency net "ddrclk90" 300.000000 mhz ; input_setup port "ddrdata_0" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_1" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_2" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_3" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_4" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_5" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_6" 0.800000 ns clknet "ddrclk90" ; input_setup port "ddrdata_7" 0.800000 ns clknet "ddrclk90" ; block asyncpaths ;
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-32 appendix e. list of compatible ddr sdram below are the criteria used to list the ddr sdram part numbers. 1. the memory device should support one dqs strobe for every eight dq data bits. 2. 4-bit, 8-bit and 16-bit con?urations. for 16-bit con?urations, each data byte must have an independent dqs strobe. 3. the memory device uses sstl2 i/o interface standard. 4. data transfer rate ddr400, ddr333 or ddr266 for latticeecp/ec devices and ddr333 or ddr266 for latticexp devices. 5. clock transfer rate of 200mhz, 167mhz or 133mhz for latticeecp/ec devices and 167mhz or 133mhz for latticexp devices. table 10-9 lists the ddr sdram part numbers that can be used with the latticeecp/ec and latticexp devices. please note these part numbers are chosen based on the criteria stated above and have not necessary been vali- dated in hardware. table 10-9. list of compatible ddr sdram ddr sdram vendor part number con?uration max data rate clock speed micron 128mb mt46v32m4tg 32mx4 ddr266 133mhz micron 128mb mt46v16m8tg 16mx8 ddr333 ddr266 167mhz 133mhz micron 128mb mt46v8m16tg 8mx16 ddr266 133mhz micron 256mb mt46v64m4fg 64mx4 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 256mb mt46v64m4tg 64mx4 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 256mb mt46v32m8fg 32mx8 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 256mb mt46v32m8tg 32mx8 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 256mb mt46v16m16fg 16mx16 ddr266 133mhz micron 256mb mt46v16m16tg 16mx16 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 512mb mt46v128m4fn 128mx4 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 512mb mt46v128m4tg 128mx4 ddr266 133mhz micron 512mb mt46v64m8fn 64mx8 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 512mb mt46v64m8tg 64mx8 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 512mb mt46v32m16fn 32mx16 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-33 micron 512mb mt46v32m16tg 32mx16 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz micron 1gb mt46v256m4tg 256mx4 ddr266 133mhz micron 1gb mt46v128m8tg 128mx8 ddr266 133mhz micron 1gb mt46v64m16tg 64mx16 ddr333 ddr266 167mhz 133mhz samsung 128mb e die k4h280438e-tc/lb3 32mx4 ddr333 167mhz k4h280838e-tc/lb3 16mx8 ddr333 167mhz k4h281638e-tc/lb3 8mx16 ddr333 167mhz samsung 256 mb e-die k4h560438e-tc/lb3 64mx4 ddr333 167mhz k4h560438e-nc/lb3 64mx4 ddr333 167mhz k4h560438e-gc/lb3, cc 64mx4 ddr333 ddr400 167mhz 200mhz k4h560838e-tc/lb3, cc 32mx8 ddr333 ddr400 167mhz 200mhz k4h560838e-nc/lb3, cc 32mx8 ddr333 ddr400 167mhz 200mhz k4h560838e-gc/lb3, cc 32mx8 ddr333 ddr400 167mhz 200mhz samsung 512mb b die k4h510838b-tc/lb3, cc 64mx8 ddr333 ddr400 167mhz 200mhz k4h510838b-nc/lb3, cc 64mx8 ddr333 ddr400 167mhz 200mhz k4h511638b-tc/lb3, cc 32mx16 ddr333 ddr400 167mhz 200mhz k4h510438b-tc/lb3 128mx4 ddr333 167mhz k4h510438b-nc/lb3 128mx4 ddr333 167mhz in?eon 128mb hyb25d128400at 32mx4 ddr266 133mhz hyb25d128400ct 32mx4 ddr266 133mhz hyb25d128400ce 32mx4 ddr266 133mhz hyb25d128800at 16mx8 ddr266 133mhz hyb25d128800ct 16mx8 ddr333 167mhz hyb25d128800ce 16mx8 ddr333 167mhz hyb25d128160at 8mx16 ddr333 ddr266 167mhz 133mhz hyb25d128160ct 8mx16 ddr333 ddr400 167mhz 200mhz hyb25d128160ce 8mx16 ddr333 ddr400 167mhz 200mhz hyb25d128160cc 8mx16 ddr333 167mhz table 10-9. list of compatible ddr sdram (continued) ddr sdram vendor part number con?uration max data rate clock speed
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-34 in?eon 256mb hyb25d256400bt 64mx4 ddr266 133mhz hyb25d256400ct 64mx4 ddr266 133mhz hyb25d256400ce 64mx4 ddr266 133mhz hyb25d256800bt 32mx8 ddr333 167mhz hyb25d256800ct 32mx8 ddr333 167mhz hyb25d256800ce 32mx8 ddr333 ddr400 167mhz 200mhz hyb25d256160bt 16mx16 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz hyb25d256160ct 16mx16 ddr333 ddr400 167mhz 200mhz hyb25d256160ce 16mx16 ddr333 ddr400 167mhz 200mhz hyb25d256400bc 64mx16 ddr400 ddr333 ddr266 200mhz 167mhz 133mhz hyb25d256400cf 64mx16 ddr333 167mhz hyb25d256400cc 64mx16 ddr333 167mhz hyb25d256160bc 16mx16 ddr333 ddr266 167mhz 133mhz hyb25d256160cc 16mx16 ddr333 ddr400 167mhz 200mhz in?eon 512mb hyb25d512400at 128mx4 ddr266 133mhz hyb25d512400bt 128mx4 ddr333 167mhz hyb25d512400be 128mx4 ddr333 167mhz hyb25d1g400bg 256mx4 ddr266 133mhz hyb25d512800at 64mx8 ddr333 ddr266 167mhz 133mhz hyb25d512800bt 64mx8 ddr333 ddr400 167mhz 200mhz hyb25d512800be 64mx8 ddr333 ddr400 167mhz 200mhz hyb25d512160at 32mx16 ddr333 ddr266 167mhz 133mhz hyb25d512160bt 32mx16 ddr333 ddr400 167mhz 200mhz hyb25d512160be 32mx16 ddr333 ddr400 167mhz 200mhz hyb25d512400bc 128mx4 ddr333 ddr400 167mhz 200mhz hyb25d512400bf 128mx4 ddr333 ddr400 167mhz 200mhz hyb25d512800bc 64mx8 ddr333 167mhz hyb25d512800bf 64mx8 ddr333 ddr400 167mhz 200mhz hyb25d512160bc 32mx16 ddr333 ddr400 167mhz 200mhz hyb25d512160bf 32mx16 ddr333 ddr400 167mhz 200mhz table 10-9. list of compatible ddr sdram (continued) ddr sdram vendor part number con?uration max data rate clock speed
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-35 appendix f. ddr400 interface using the latticeec evaluation board the ddr400 interface was implemented using the latticeec20 device on the latticeec advanced evaluation board. figures 10-21, 10-22 and 10-23 show the read, write and write to read transition operations running at 200mhz. for more information on the evaluation board, refer to latticeec advanced evaluation board users guide available on the lattice web site at www .latticesemi.com . figure 10-21. read function running at 200mhz note: an extra read command is implemented in the latticeec20 device to protect the data during postamble. this extra read is not required for other latticeec devices. refer to the dqs postamble section of this document for more information.
latticeecp/ec and latticexp lattice semiconductor ddr usage guide 10-36 figure 10-22. write function running at 200mhz figure 10-23. write to read transition running at 200mhz note: an extra read command is implemented in the latticeec20 device to protect the data during postamble. this extra read is not required for other latticeec devices. refer to the dqs postamble section of this document for more information.
www.latticesemi.com 11-1 tn1049_04.1 september 2006 technical note tn1049 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. introduction as clock distribution and clock skew management become critical factors in overall system performance, the phase locked loop (pll) is increasing in importance for digital designers. lattice incorporates its sysclock pll tech- nology in the latticeecp, latticeec and latticexp device families to help designers manage clocks within their designs. the pll components in the latticeecp/ec and latticexp device families share the same architec- ture. this technical note describes the features and functionalities of the plls and their con?uration in the isplever design tool. figure 11-1 shows the block diagram of the pll. figure 11-1. latticeecp/ec and latticexp sysclock pll block diagram features clock synthesis phase shift/duty cycle selection internal and external feedback dynamic delay adjustment no external components required lock detect output functional description pll divider and delay blocks input clock (clki) divider the clki divider is used to control the input clock frequency into the pll block. it can be set to an integer value of 1 to 16. the divider setting directly corresponds to the divisor of the output clock. the input and output of the input divider must be within the input and output frequency ranges speci?d in the device data sheet. feedback loop (clkfb) divider the clkfb divider is used to divide the feedback signal. effectively, this multiplies the output clock, because the divided feedback must speed up to match the input frequency into the pll block. the pll block increases the out- put frequency until the divided feedback frequency equals the input frequency. like the input divider, the feedback clki divider clkfb divider delay adjust phase & frequency detector voltage controlled oscillator clkop divider clkok divider phase/duty select lock detect loop filter rst clkfb clki lock clkop clkos clkok ddaozr ddaolag ddaodel[2:0] ddamode ddaizr ddailag ddaidel[2:0] internal feedback from clkop divider output latticeecp/ec and latticexp sysclock pll design and usage guide
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-2 loop divider can be set to an integer value of 1 to 16. the input and output of the feedback divider must be within the input and output frequency ranges speci?d in the device data sheet. delay adjustment the delay adjust circuit provides programmable clock delay. the programmable clock delay allows for step delays in increments of 250ps (nominal) for a total of 2.00ns lagging or leading. the time delay setting has a tolerance. see device data sheet for details. under this mode, clkop, clkos and clkok are identically affected. the delay adjustment has two modes of operation: static delay adjustment ?in this mode, the user-selected delay is con?ured at power-up. dynamic delay adjustment (dda) ?in this mode, a simple bus is used to con?ure the delay. the bus signals are available to the general purpose fpga. output clock (clkop) divider the clkop divider serves the dual purposes of squaring the duty cycle of the vco output and scaling up the vco frequency into the 420mhz to 840mhz range to minimize jitter. refer to table 11-3 for clkop divider value. clkok divider the clkok divider feeds the global clock net. it divides the clkop signal of the pll by the value of the divider. it can be set to values of 2, 4, 6,....126,128. pll inputs and outputs clki input the clki signal is the reference clock for the pll. it must conform to the speci?ations in the data sheet in order for the pll to operate correctly. the clki can be derived from a dedicated dual-purpose pin or from routing. rst input the pll reset occurs under two conditions. at power-up an internal power-up reset signal from the con?uration block resets the pll. the user controlled pll reset signal rst is provided as part of the pll module that can be driven by an internally generated reset function or a pin. this rst signal resets all internal pll counters. when rst goes inactive, the pll will start the lock-in process, and will take the t lock time to complete the pll lock. note: for latticeecp/ec, rst must be asserted to re-start the locking process after losing lock. refer to the latticeecp/ec family data sheet for the rst pulse width requirement. for latticexp, rst may be tied to gnd. figure 11-2 shows the timing diagram of the rst input. figure 11-2. rst input timing diagram clkfbk input the feedback signal to the pll, which is fed through the feedback divider can be derived from the global clock net, a dedicated dual-purpose pin, or directly from the clkop divider. feedback must be supplied in order for the pll to synchronize the input and output clocks. external feedback allows the designer to compensate for board-level clock alignment. clkop output the sysclock pll main clock output, clkop, is a signal available for selection as a primary clock. t rst t lock rst lock
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-3 clkos output with phase and duty cycle select the sysclock pll auxiliary clock output, clkos, is a signal available for selection as a primary clock. the clkos is used when phase shift and/or duty cycle adjustment is desired. the programmable phase shift allows for different phase in increments of 45?to 315? the duty select feature provides duty select in 1/8th of the clock period. clkok output with lower frequency the clkok is used when a lower frequency is desired. it is a signal available for selection as a primary clock. dynamic delay control i/o ports refer to table 11-1 and table 11-6 for detailed information. lock output the lock output provides information about the status of the pll. after the device is powered up and the input clock is valid, the pll will achieve lock within the speci?d lock time. once lock is achieved, the pll lock signal will be asserted. if, during operation, the input clock or feedback signals to the pll become invalid, the pll will lose lock. pll rst must be applied to re-synchronize the pll to the reference clock. the lock signal is available to the fpga routing to implement generation of rst. pll attributes the pll utilizes several attributes that allow the con?uration of the pll through source constraints. the following section details these attributes and their usage. fin the input frequency can be any value within the speci?d frequency range based on the divider settings. clki_div, clkfb_div, clkop_div, clkok_div these dividers determine the output frequencies of each output clock. the user is not allowed to input an invalid combination; determined by the input frequency, the dividers, and the pll speci?ations. frequency_pin_clki, frequency_pin_clkop and frequency_pin_clkok these output clock frequencies determine the divider values. fdel the fdel attribute is used to pass the delay adjustment step associated with the output clock of the pll. this allows the user to advance or retard the output clock by the step value passed multiplied by 250ps(nominal). the step ranges from -8 to +8 resulting the total delay range to +/- 2ns. phaseadj the phaseadj attribute is used to select coarse phase shift for clkos output. the phase adjustment is pro- grammable in 45?increments. duty the duty attribute is used to select the duty cycle for clkos output. the duty cycle is programmable at 1/8 of the period increment. fb_mode there are three sources of feedback signals that can drive the clkfb divider: internal, clocktree and external feedback. clocktree feedback is used by default. internal feedback takes the clkop output at clkop divider out- put before the clocktree to minimize the feedback path delay. the external feedback is driven from the pin. delay_cntl this attribute is designed to select the delay adjustment mode. if the attribute is set to ?ynamic the delay con- trol switches between dynamic and static depending upon the input logic of ddamode pin. if the attribute is set to ?tatic? dynamic delay inputs are ignored in this mode.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-4 latticeecp/ec and latticexp pll primitive de?itions the pll primitive name is ehxpllb. figure 11-3 shows the latticeecp/ec and latticexp pll primitive library symbol. some features and i/os are optional as described in table 11-1 and table 11-2. figure 11-3. latticeecp/ec and latticexp pll primitive symbol table 11-1. latticeecp/ec and latticexp pll i/o de?itions pll attributes de?itions the ehxpllb can be con?ured through attributes in the source code. the following section details these attributes and their usage. signal i/o description optional clki i pll reference clock input. from internal logic or dedicated clock pin. no clkfb 1 i feedback clock input. from internal node, clkop or dedicated pin. no rst i ? to reset pll no clkop o pll output clock to clock tree no clkos o pll output clock to clock tree with optional phase shift/duty cycle yes clkok o pll output clock to clock tree through k-divider for lower frequency yes lock 2 o ? indicates pll locked to clki yes ddamode i dda mode. ?? pin control (dynamic), ?? fuse control (static) yes ddaizr i dda delay zero. ? delay=0, ?? delay=[ddilag+ddaidel]. yes ddailag i dda lag/lead. ?? lead, ?? lag. yes ddaidel i dda delay ye s ddaozr o dda delay zero output yes ddaolag o dda lag/lead output yes ddaodel[2:0] o dda delay output yes 1. when internal feedback or clocktree feedback is selected in the ipexpress gui, software uses clkop as the source of clkfb. c lkos is not recommended as the source of clkfb even in external feedback mode. 2. modelsim simulation models take two to four clock cycles from rst release to lock high. table 11-2. latticeecp/ec and latticexp pll attributes user accessible ipexpress gui access attribute name preference language support preference editor support value default value units clki frequency y frequency_pin_clki n n note 5 100 mhz clkop frequency y frequency_pin_clkop n n note 5 100 mhz clkok frequency y frequency_pin_clkok n n note 5 50 mhz clkop frequency tolerance y n n 0.0, 0.1, 0.2, 0.5, 1.0, 2.0, 5.0, 10.0 0.0 % clkop actual frequency y n n mhz clkok frequency tolerance y n n 0.0, 0.1, 0.2, 0.5,1.0, 2.0, 5.0, 10.0 0.0 % ehxpllb rst clki clkfb ddamode ddaizr ddailag ddaidel2 ddaidel1 ddaidel0 clkop clkos clkok lock ddaozr ddaolag ddaodel2 ddaodel1 ddaodel0
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-5 fdel settings there are four ways the user can enter the desired fdel value. 1. although the fdel entry is not available in the ipexpress gui, the module generated by ipexpress includes the attribute with default value, ?? users can replace it with a desired value. example of source code with default fdel value: attribute fdel of ehxpll_mod_0_0 : label is "0"; generic map (? fdel=>"0", ? ") 2. preference file: user may specify the preference in the preference ?e. example: asic "fdel_code_0_0" type "ehxpllb" fdel="-2" ; 3. pre-map preference editor: users can enter the fdel value in the pre-map preference editor as shown in figure 11-4. clkok actual frequency y n n mhz clki divider setting y clki_div 4, 6 y n 1 to 16 (1 to 15) 1 clkfb divider setting y clkfb_div 6 y n 1 to 16 (1 to 15) 1 clkop divider setting y clkop_div 6 y n note 3 8 2 (4 or 6) clkok divider setting y clkok_div y n 2, 4, 6,..,126, 128 2 fine delay adjust n fdel y y -8 to 8 0 ps coarse phase shift selection (o) y phaseadj y n 0, 45, 90...315 0 degrees duty cycle selection (1/8 increment) y duty y n 1 to 7 4 delay control y delay_cntl1 y n dynamic/static static feedback mode y fb_mode n n internal/clocktree/external clocktree clkos select y n n clkok select y n n 1. dynamic: this mode switches delay control between dynamic and static depending upon the input logic of the ddamode pin. static: this is static control only mode. 2. the clkop_div value is calculated to maximize the f vco within the speci?d range. for latticexp devices, if clkos is not used, the default value is 6. if clkos is used, the value is 4. 3. the clkop divider values are 2, 4, 6, 8,..32 (2, 4, 6, 8..16 for latticexp devices) if clkos is not used. the clkop divider v alues are 2, 4, 8, 16, 32 (2, 4, 8,16 for latticexp devices) if clkos is used. 4. all divider settings are user transparent in frequency mode. these are user attributes in divider mode. 5. refer to data sheet for frequency limits. 6. values in parentheses are for latticexp devices. 7. this attribute is not available in the ipexpress gui. after reviewing the trace report ?e, users can determine the amount of delay that will best ? the clocking in their design. further information on fdel settings is described in the following section. table 11-2. latticeecp/ec and latticexp pll attributes (continued) user accessible ipexpress gui access attribute name preference language support preference editor support value default value units
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-6 figure 11-4. pre-map preference editor 4. epic device editor: users can edit their preferences in the epic device editor as shown in figure 11-5. figure 11-5. epic preferences edit window dynamic delay adjustment the dynamic delay adjustment is controlled by the ddamode input. when the ddamode input is set to ?? the delay control is handled through the inputs, ddaizr, ddailag and ddaidel(2:0). for this mode, the attribute ?elay_cntl must be set to ?ynamic? table 11-3 shows the delay adjustment values based on the attribute/input settings. in this mode, the pll may come out of lock due to the abrupt change of phase. rst must be asserted to re-lock the pll. upon de-assertion of rst, the pll will start the lock-in process and will take the t lock time to complete the pll lock.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-7 table 11-3. delay adjustment pll usage in ipexpress including sysclock plls in a design the sysclock pll capability can be accessed through the ipexpress gui. the following section describes the usage of ipexpress. ipexpress usage the latticeecp/ec and latticexp pll is fully supported in ipexpress in the isplever software. ipexpress allows the user to de?e the desired pll using a simple, easy-to-use gui. following de?ition, a vhdl or verilog module that instantiates the desired pll is created. this module can be included directly in the users design. figure 11-6 shows the main window when pll is selected. the only entry required in this window is the module name. after entering the module name, clicking on ?ustomize will open the ?on?uration window as shown in figure 11-7. ddamode = 1: dynamic delay adjustment delay 1 t dly = 250ps (nominal) ddamode = 0 ddaizr ddailag ddaidel[2:0] equivalent fdel value 0 1 111 lead 8 t dly -8 0 1 110 lead 7 t dly -7 0 1 101 lead 6 t dly -6 0 1 100 lead 5 t dly -5 0 1 011 lead 4 t dly -4 0 1 010 lead 3 t dly -3 0 1 001 lead 2 t dly -2 0 1 000 lead 1 t dly -1 1 don? care don? care no delay 0 0 0 000 lag 1 t dly 1 0 0 001 lag 2 t dly 2 0 0 010 lag 3 t dly 3 0 0 011 lag 4 t dly 4 0 0 100 lag 5 t dly 5 0 0 101 lag 6 t dly 6 0 0 110 lag 7 t dly 7 0 0 111 lag 8 t dly 8 note: t dly = unit delay time = 250 ps (nominal). see the data sheet for the tolerance of this delay
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-8 figure 11-6. ipexpress main window con?uration tab the con?uration tab lists all user accessible attributes. default values are set initially. there are two modes in the con?uration tab which can be used to con?ure the pll, frequency mode and divider mode. frequency mode : in this mode, the user enters input and output clock frequencies and the software calculates the divider settings for the user. if the output frequency the user entered is not achievable, the nearest frequency will be displayed in the ?ctual text box. after input and output frequencies are entered, clicking the ?alculate button will display the divider values. if the desired output frequency is not achievable with the given frequency tolerance, the software generates an error. users may increase the frequency tolerance or change the output frequencies. figure 11-7 shows the con?uration tab window.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-9 figure 11-7. con?uration tab divider mode : in this mode, the user sets the input frequency and divider settings. it is assumed the user is famil- iar with the pll operation. the user must choose the clkop divider value to maximize the f vco to achieve opti- mum pll performance. after input frequency and divider settings are set, clicking the ?alculate button will display the output frequencies. if the divider settings are out of the pll speci?ation, the software will generate an error. ehxpllb example projects isplever provides example pll projects for ?st time pll users. in the isplever project navigator, go to the file menu and select open examples... . select the fpga folder. the latticeec and latticexp folders include pll example projects in both verilog and vhdl.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-10 equations for generating input and output frequency ranges the values of f in, f out and f vco are the absolute frequency ranges for the pll. the values of f inmin, f inmax, f out- min and f outmax are the calculated frequency ranges based on the divider settings. these calculated frequency ranges become the limits for the speci? divider settings used in the design. table 11-4. frequency limits the divider names are abbreviated with legacy names as: clki divider:m clkfb divider:n clkop divider:v clkok divider:k for use in the equations below. f vco constraint from the loop: f out = f in * (n/m) (1) from the loop: f vco = f out * v (2) substitute (1) in (2) yields: f vco = f in * (n/m) * v (3) arrange (3): f in = (f vco / (v*n))*m (4) from equation (4): f inmin = ((f vcomin /(v*n))*m (5) f inmax = (f vcomax /(v*n))*m (6) f pfd constraint from the loop: f pfd = f in / m (7) f in = f pfd * m f inmin = f pfdmin * m = 25 * m (assume f pfdmin = 25) (8) equation (5) becomes: parameter latticeecp/ec latticexp f in note 1 f out note 1 f outk note 1 f vco (hz) note 1 clki divider 1 to 16 1 to 15 clkfb divider 1 to 16 1 to 15 clkop divider see table 11-2 clkok divider 2, 4, 6, 8,.. ,126, 128 maximum (n*v) 32 30 f pfd (f in /m) (hz) note 1 note: refer to data sheet for the latest data.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-11 f inmin = ((f vcomin / (v*n))*m, if below 25 * m round up to 25 * m (9) from the loop: f inmax = f pfdmax * m = 420 * m (10) assume f inmax = 420 equation (6) becomes: f inmax = (f vcomax / (v*n))*m, if above 420 round down to 420 (11) from equation (1): f outmin = f inmin * (n/m), if below 25 * n round up to 25 * n (12) f outmax = f inmax * (n/m), if above 420 round down to 420 (13) f outkmin = f outmin / k f outkmax = f outmax / k clock distribution in latticeecp/ec and latticexp the clock inputs are selected from external i/os, the sysclock plls or general routing. these clock inputs are fed through the chip via a clock distribution system. latticeecp/ec and latticexp devices provide a quadrant-based primary and secondary clock structure. primary clock sources and distribution each quadrant has four primary clock nets: clk0, clk1, clk2 and clk3. clk2 and clk3 provide dynamic clock selection (dcs) capability. figure 11-8 illustrates the block diagram of the primary clock distribution. figure 11-8. primary clocks and center switch boxes note: two plls are available in latticeecp/ec/xp-6 or smaller devices. primary clocks in center switch box pll*: for latticeecp/ec/xp-10 and larger de v ices quadrant tl quadrant tr quadrant bl quadrant br pclkt7 pclkt2 pll* clkop clkos clkok pll clkop clkos clkok pll* clkop clkos clkok pll clkop clkos clkok general ro u ting general ro u ting clk0 clk1 clk2 clk3 dcs dcs dcs 16:1 dcs clk3 clk2 clk1 clk0 general ro u ting general ro u ting clk0 clk1 clk2 clk3 16:1 16:1 16:1 16:1 12:1 12:1 12:1 12:1 12:1 12:1 12:1 12:1 dcs dcs 16:1 clk3 clk2 clk1 clk0 16:1 16:1 12:1 12:1 12:1 12:1 12:1 12:1 12:1 12:1 dcs dcs pclkt0 pclkt5
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-12 note on the primary clock the clkop must be used as the feedback source to optimize the pll performance. most designers use the pll for the clock tree injection removal mode and the clkop should be assigned as the primary clock. this is done automatically by the software unless the user speci?s otherwise. clkop can route to clk0 and clk1 only. clkos/clkok can route to all primary clocks (clk0 to clk3). when clk2 or clk3 is used as a primary clock and there is only one clock input to the dcs, the dcs is assigned as a buffer mode by the software. please see the dcs section of this document for further information. clock net preferences there are two clock nets, primary clock and secondary clock. as illustrated in figure 11-9, users can set each clock to the desired clock net in the pre-map preference editor or write in the preference file as shown in the examples below. primary-pure and primary-dcs primary clock net can be assigned to either primary-pure (clk0 and clk1) or primary-dcs (clk2 and clk3). syntax example use primary dcs net "bf_clk"; global primary clock and quadrant primary clock global primary clock if a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock. there are two global primary/pure clocks and two global primary/dcs clocks available. quadrant primary clock any primary clock may be assigned to a quadrant clock. the clock may be assigned to a single quadrant or to two adjacent quadrants (not diagonally adjacent). when the quadrant clock net is used, users must ensure that the registers each clock drives can be assigned in that quadrant without any routing issues. with the quadrant primary clocking scheme, the maximum number of primary clocks is 16 as long as all the pri- mary clock sources are avaialble. syntax example use primary pure net "bf_clk" quadrant_tl;
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-13 figure 11-9. clock preferences in the pre-map preference editor secondary clock sources and distribution latticeecp/ec and latticexp devices support quadrant base secondary clocks. figure 11-10 describes the sec- ondary clock arrangement. figure 11-10. secondary clock center switch box limitations on secondary clock availability as illustrated in figure 11-11, three secondary clocks are shared with clk, ce and lsr. this routing scheme limits the secondary clocks available per quadrant base to three, which results in a maximum of 12 available secondary clocks per device. figure 11-11 illustrates the primary and secondary clock distribution structure of the pfus. quadrant tr scondary clock trunk quadrant bl scondary clock trunk quadrant br scondary clock trunk pclkt7 pclkt2 pcl kt0 pcl kt5 general ro u ting 4 general ro u ting 4 general ro u ting 4 quadrant tr scondary clock trunk general ro u ting 4 secondary clocks in center s w itch box sclk0 sclk1 sclk2 sclk3 sclk3 sclk2 sclk1 sclk0 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1 sclk0 sclk1 sclk2 sclk3 sclk3 sclk2 sclk1 sclk0 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1 8 :1
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-14 lfec6/lfxp6 and smaller devices have limited routing resources and can implement a maximum of nine second- ary clocks per device. figure 11-11. primary clock and secondary clock/ce/lsr distribution dynamic clock selection (dcs) dcs is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of when the enable signal is toggled. the dcs blocks are located in pairs at the center of each side of the device. thus, there are eight of them in every device. table 11-5. dcs i/o i/o name description input sel input clock select clk0 primary clock input 0 clk1 primary clock input 1 output dcsout to primary clock primary clock 25:1 secondary clock /ce/lsr 4 3 pfu clk(0:3) pclk0 pclk1 pclk2 pclk3 sclk0/ce/lsr sclk2/ce/lsr sclk3/ce/lsr sclk1/ce/lsr 3 20:1 pfu ce(0:3) pfu lsr(0:3) 3 secondary clock/ce/lsr net 20 :1 local local local secondary clock /ce/lsr secondary clock /ce/lsr primary clock net
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-15 table 11-6. dcs attributes figure 11-12. dcs primitive symbol dcs waveforms the dcsout waveform timing is described in figure 11-13 for each mode. the ?os and ?eg modes describe dcsout timing at both the falling and rising edges of sel. figure 11-13. dcs waveforms dcs mode = pos at the rising edge (pos) of sel, the dcsout changes from clk0 to clk1. this mode is the default mode. attribute name description output value sel=0 sel=1 dcs mode rising edge triggered, latched state is high clk0 clk1 pos (default) falling edge triggered, latched state is low clk0 clk1 neg sel is active high, disabled output is low 0 clk1 high_low sel is active high, disabled output is high 1 clk1 high_high sel is active low, disabled output is low clk0 0 low_low sel is active low, disabled output is high clk0 1 low_high buffer for clk0 clk0 clk0 clk0 buffer for clk1 clk1 clk1 clk1 dcs dcsout clk0 sel clk1 clk0 clk1 sel dcsout sel falling edge: - wait for clk1 rising edge, latch output & remain high - switch output at clk0 rising edge sel rising edge: - wait for clk0 rising edge, latch output & remain high - switch output at clk1 rising edge dcs mode = pos
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-16 dcs mode = neg at the falling edge (neg) of sel, the dcsout changes from clk0 to clk1. dcs mode = high_low sel is active high (high) to select clk1, and the disabled output is low. dcs mode = low_low sel is active low (low) to select clk0, and the disabled output is low. dcs mode = high_high sel is active high (high) to select clk1, and the disabled output is high. dcs mode = low_high sel is active low (low) to select clk0, and the disabled output is high. clk0 clk1 sel dcsout sel falling edge: - wait for clk1 falling edge, latch output & remain low - switch output at clk0 falling edge sel rising edge: - wait for clk0 falling edge, latch output & remain low - switch output at clk1 falling edge dcs mode = neg clk1 sel dcsout - switch low at clk1 falling edge. - if sel is low, output stays low at on clk1 rising edge. sel must not change during setup prior to rising clock. dcs mode = high_low clk0 sel dcsout - switch low at clk0 falling edge. - if sel is high, output stays low at on clk0 rising edge. dcs mode = low_low
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-17 use of dcs with pll the four pll clkop sources reach clk0 and clk1 of the quadrant clock. when using the dcs, the pll needs a free-running feedback path to keep the pll in lock. the user should use clkop as this feedback path, and clkos as the input into the dcs. clkop does not reach clk2 or clk3 to prevent the user from using the pll improperly with dcs. see figure 11-14. figure 11-14. implementation of dynamic clock select for a pll clock (must use both clkop and clkos) other design considerations jitter considerations the clock output jitter speci?ations assume that the reference clock is free of jitter. even if the clock source is clean, there are a number of sources that place noise in the pll clock input. while intrinsic jitter is not avoidable, there are ways to minimize the input jitter and output jitter. signal inputs that share the same i/o bank with pll clock inputs are preferably less noisy inputs and slower switching signals. try to avoid placing any high speed and noisy signals in the same i/o bank with clock signals if possible. use differential signaling if possible. when external feedback is used, the pcb path must be well designed to avoid re?ction as well as noise coupling from adjacent signal sources. a shorter pcb feedback path length does not necessarily reduce feedback input jit- ter. simulation limitations simulation does not compensate for external delays and dividers in the feedback loop. the lock signal is not simulated according to the t lock speci?ation. the lock signal will appear active shortly after the simulation begins, but will remain active throughout the simulation. the jitter speci?ations are not included. clk1 sel dcsout - switch high at clk1 rising edge. - if sel is low, output stays low high on clk1 falling edge. dcs mode = high_high clk0 sel dcsout - switch high at clk0 rising edge. - if sel is high, output stays high on clk0 falling edge. dcs mode = low_high clkop clkos (set 0 ) clkfb clki pll clk2 clk0 d c s clk2 isb clk2 isb clk0 isb
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-18 pcb layout recommendations for vccpll and gndpll if separate pins are available it is best to connect vccpll to vcc at a single point using a ?ter and to create a separate gndpll plane directly under it (tied via a single point to gnd). separate islands for both vccpll and gndpll are recommended if applicable. dcs usage with verilog module dcs(clk0,clk1,sel,dcsout); input clk0, clk1, sel; output dcsout; dcs dcsinst0 (.sel(sel),.clk0(clk0),.clk1(clk1),.dcsout(dcsout)); defparam dcsinst0.dcsmode = "clk0"; endmodule dcs usage with vhdl component dcs -- synthesis translate_off generic ( dcsmode : string := "pos" ); -- synthesis translate_on port ( clk0 :in std_logic; clk1 :in std_logic; sel :in std_logic; dcsout :out std_logic ); end component; attribute dcsmode : string; attribute dcsmode of dcsinst0 : label is "pos"; begin dcsinst0: dcs -- synthesis translate_off generic map( dcsmode => "pos" ) -- synthesis translate_on port map ( sel => clksel, clk0 => dcsclk0, clk1 => sysclk1, dcsout => dcsclk );
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-19 technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history date version change summary june 2004 01.0 initial release. october 2004 01.1 rst description with timing diagram added. primitive ?ake_on_lock removed. added rst input in epllb. fin min 33 replaced with 25. fb_mode default = clocktree clkop_div values for ehxpllb 2, 4, 8,16, 32. december 2004 02.0 appendices c and d integrated to body of the document. dcs source code example moved to appendix a. january 2005 03.0 latticexp information added. figures 6 and 7 updated. clkop_freq, clkok_freq user attributes added. fb_mode added. october 2005 04.0 clock distribution section added. example code section removed and referred to help ?e. gui screen shots updated. mm/ip manager renamed as ipexpress. epllb de?ition section removed. clkos/clkok select attributes added. september 2006 04.1 detailed clock distribution information added.
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-20 appendix a. clock preferences a few key clock preferences are introduced below. refer to the ?elp ?e for other preferences and detailed infor- mation. asic the following preference command assigns a phase of 90?to the cimdlla clkop. asic "my_pll" type "exhxpllb" clkos_phase=90; frequency the following physical preference command assigns a frequency of 100 mhz to a net named clk1. frequency net "clk1" 100 mhz; the following preference speci?s a hold margin value for each clock domain. frequency net "rx_clka_cmos_c" 100.000 mhz hold_margin 1 ns; maxskew the following command assigns a maximum skew of 5 ns to a net named netb. maxskew net "netb" 5 ns; multicycle the following command will relax the period to 50 ns for the path starting at compa to compb (net1). multicycle "path1" start comp "compa" end comp "compb" net "net1" 50 ns ; period the following command assigns a clock period of 30 ns to the port named clk1. period port "clk1" 30 ns; prohibit this command prohibits the use of a primary clock to route a clock net named bf_clk. prohibit primary net "bf_clk"; clock_to_out speci?s a maximum allowable output delay relative to a clock. below are two preferences using both the clkport and clknet keywords showing the corresponding scope of trace reporting. the clknet will stop tracing the path before the pll, so you will not get pll compensation timing numbers. clock_to_out port "rxaddr_0" 6.000000 ns clknet "pll_rxclk" ; the above preference will yield the following clock path:
latticeecp/ec and latticexp lattice semiconductor sysclock pll design and usage guide 11-21 physical path details: clock path pll_inst/pll_utp_0_0 to pfu_33: name fanout delay (ns) site resource route 49 2.892 ulppll.mclk to r3c14.clk0 pll_rxclk -------- 2.892 (0.0 % logic, 100.0 % route), 0 logic levels. if clkport is used, the trace is complete back to the clock port resource and provides pll compensation timing numbers. clock_to_out port "rxaddr_0" 6.000000 ns clkport "rxclk" ; the above preference will yield the following clock path: clock path rxclk to pfu_33: name fanout delay (ns) site resource in_del --- 1.431 d5.pad to d5.inck rxclk route 1 0.843 d5.inck to ulppll.clkin rxclk_c mclk_del --- 3.605 ulppll.clkin to ulppll.mclk pll_inst/pll_utp_0_0 route 49 2.892 ulppll.mclk to r3c14.clk0 pll_rxclk -------- 8.771 (57.4 % logic, 42.6 % route), 2 logic levels. input_setup speci?s an setup time requirement for input ports relative to a clock net. input_setup port "datain" 2.000000 ns hold 1.000000 ns clkport "clk" pll_phase_back ; pll_phase_back this preference is used with input_setup when the user wants a trace calculation based on the previous clock edge. this preference is useful when setting the pll output phase adjustment. since there is no negative phase adjust- ment provided, the pll_phase_back preference works as if negative phase adjustment is available. for example: if phase adjustment of -90?of clkos is desired, the user can set the phase to 270?and set the input_setup preference with pll_phase_back.
www.latticesemi.com 12-1 tn1052_02.2 november 2006 technical note tn1052 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. introduction one of the requirements when using fpga devices is the ability to calculate power dissipation for a particular device used on a board. lattices isplever design tools include a power calculator tool which allows designers to calculate the power dissipation for a given device. this technical note explains how to use power calculator to calculate the power consumption of lattice devices. general guidelines to reduce power consumption are also included. power supply sequencing and hot socketing latticeecp, latticeec and latticexp devices have eight sysio buffer banks in addition to the v cc, v ccaux and v ccj power supplies; each is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ), and two voltage references v ref1 and v ref2 resources allowing each bank to be com- pletely independent from each other. the latticeecp/ec and latticexp devices are designed to ensure predictable behavior during power-up and power-down. power supplies can be sequenced in any order. the i/os remain in tristate until the power supply volt- age is high enough to ensure reliable operation during power up and power-down sequences and the leakage into i/o pins is controlled to within speci?d limits. refer to the typical i/o behavior during power-up and hot socketing sections of the device data sheet for more details. power calculator hardware assumptions the power consumption for a device can be coarsely broken down into the dc portion and the ac portion. the power calculator reports the power dissipation in terms of: 1. dc portion of the power consumption. 2. ac portion of the power consumption. the dc power (or the static power consumption) is the total power consumption of the used and unused resources. these components are ?ed for each resource used and depend upon the number of resource units utilized. the dc component also includes the static power dissipation for the unused resources of the device. the ac portion of power consumption is associated with the used resources and it is the dynamic part of the power consumption. its power dissipation is directly proportional to the frequency at which the resource is running and the number of resource units used. power calculator power calculator is a powerful tool which allows users to make an estimate of the power consumption at two differ- ent levels: 1. estimate of the utilized resources before completing place and route 2. post place and route design for ?st level estimation, the user provides estimates of device usage in the power calculator wizard and the tool provides a rough estimate of the power consumption. the second level is a more accurate approach where the user imports the actual device utilization by importing the post place and route netlist (ncd) ?e. estimating power using the power calculator for latticeecp/ec and latticexp devices
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-2 power calculator equations the power equations used in the power calculator have the following general form: total dc power (resource) = total dc power of used portion + total dc power of unused portion = [dc leakage per resource when used * n resource ] + [dc leakage per resource when unused * (n total resource - n resource )] where: n total resource is the total number of resources in a device. n resource is the number of resources used in the design. the total dc power consumption for all the resources as per the design data is the sum of quiescent power and the individual dc power of the resources in the power calculator. total dc power (i ccaux ) = k resource * 500 ? + typical standby i ccaux where: kresource is the number of reference input i/o such as hstl/sstl. for lvds kre- source is number of inputs divided by two. i ccaux is a dc current that does not change with i/o toggle rate or temperature. typical standby i ccaux is found in the data sheet. the ac power, on the other hand, is governed by the equation: total ac power (resource) =k resource * f max * af resource * n resource where: n total resource is the total number of resources in a device. n resource is the number of resources used in the design. k resource is the power constant for the resource, measured in mw/mhz. f max is the maximum frequency at which the resource is running, measured in mhz. af resource is the activity factor for the resource group, as a percentage ( % ) of switching frequency. based on the above equations, if we wish to calculate the power consumption of the slice portion, it will be as fol- lows: total dc power (slice) = total dc power of used portion + total dc power of unused portion = [dc leakage per slice when used * n slice ] + [dc leakage per slice when unused * (n total slice - n slice )] total ac power (slice) =k slice * f max * af slice * n slice the dc and ac power, for a dedicated block, like dsp in latticeecp devices, is governed by the following equa- tions. total dc power (resource) = dc leakage per resource * n resource
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-3 total ac power (resource) =k resource * f max * n resource where: n resource is the total number of resources in a device. k resource is the power constant for the resource, measured in mw/mhz. f max is the maximum frequency at which the resource is running, measured in mhz. starting the power calculator the user can launch the power calculator by one of the two methods. the ?st method is by clicking the power cal- culator button in the toolbar as shown in figure 12-1. figure 12-1. starting power calculator from toolbar alternatively, users can launch the power calculator by going to the tools menu and selecting the option power calculator as shown in figure 12-2.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-4 figure 12-2. starting power calculator from tools menu the power calculator does not support some of lattices older devices. the toolbar button and menu item is only present when supported devices are selected.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-5 starting a power calculator project once the power calculator has been started, the power calculator window appears. click on file ->menu , and select new to get to the start project window, as shown in figure 12-3. figure 12-3. power calculator start project window (create new project) the start project window is used to create a new power calculator project (*.pep project). three pieces of data are input in the start project window. 1. the power calculator project name by default is same as the project navigator project name. the name can be changed, if desired. 2. project directory is where the power calculator project (*.pep) ?e will be stored. by default, the ?e is stored in the main project folder. 3. input an ncd ?e (if available) or browse to the ncd ?e in a different location.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-6 power calculator main window the main power calculator window is shown in figure 12-4. figure 12-4. power calculator main window (type view) the top pane of the window shows information about the device family, device and the part number as it appears in the project navigator. the v cc used for the power calculation is also listed. users have an option to provide the ambient temperature, and the junction temperature is calculated based on that. users can also enter values of air?w in linear feet per minute (lfm) along with heat sink to get the junction tem- perature. a table in the top part of the power calculator summarizes the currents and power consumption associ- ated with each type of power supply for the device. this also takes into consideration the i/o power supplies. in the middle pane of the window, there are two tabs: 1. power view 2. report the ?st tab is the power view. under this tab, the power calculator tool has an interactive spreadsheet type inter- face.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-7 the second and third columns, which are shaded blue in the tool, provide the dc (or static) and ac (or dynamic) power consumption, respectively. in case of the i/o, there are four columns that are shaded blue. these provide the dc and ac power for i/os for the core voltage, v cc and the i/o voltage supply, v ccio. the ?st three rows show the quiescent power for v cc, v ccaux and v ccj. these are dc power numbers for a blank device or device with no resource utilization. some of the cells are shaded yellow in the tool. these cells are editable cells and users can type in values such as frequency, activity factors and resource utilization. the second tab or the report tab is the summary of the power view. this report is in text format that provides the details of the power consumption. the ?al pane or the lower pane of the window is the log pane where users can see the log of the various opera- tions in the power calculator. figure 12-5. power calculator main window (power report view)
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-8 power calculator wizard the power calculator wizard allows users to estimate the power consumption of a design. this estimation is done before actually creating the design. the user must understand the logic requirements of the design. the wizard asks the user to provide these parameters and then estimates the power consumption of the device. to start the power calculator in the wizard mode, go to the file menu and select wizard . alternatively, click on the wizard button and get the power calculator - wizard window, as shown in figure 12-6. select the option create a new project and check the wizard check box in the power calculator start project window. users provide the project name and the project folder and click continue . since power is being estimated before the actual design, no ncd ?e is required. figure 12-6. power calculator start project window (using the new project window wizard) the next screen, as shown in figure 12-7, allows users to select the device family, device and appropriate part number. after making proper the selections, click continue . this is shown in figure 12-7.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-9 figure 12-7. power calculator wizard mode window - device selection in the following screens, as shown in figures 12-8-12-12, users can select further resources such as i/o types and provide a clock name, frequency at which the clock in running and other parameters, by selecting the appropriate resource using the pull-down type menu: 1. routing resources 2. logic 3. ebr 4. i/o 5. pll 6. clock tree the numbers in these windows refers to the number of clocks and the index corresponds to each of the clocks. by default, the clock names are clk_1, clk_2, and so on. the name of each clock can be changed by typing in the clock name text box. for each clock domain and resource users can specify parameters such as frequency, activ- ity factor, etc. users can click the create button for each clock-driven resource using the pull-down type menu. these parameters are then used in the power type view window (see figure 12-13) which can be seen by clicking finish.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-10 figure 12-8. power calculator wizard mode window - resource speci?ation - logic figure 12-9. power calculator wizard mode window - resource speci?ation - ebr
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-11 figure 12-10. power calculator wizard mode window - resource speci?ation - pll figure 12-11. power calculator wizard mode window - resource speci?ation - routing resources
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-12 figure 12-12. power calculator wizard mode window - resource speci?ation - i/os figure 12-13. power calculator wizard mode - main window
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-13 power calculator ?creating a new project without the ncd file a new project can be started without the ncd ?e by either using the wizard (as discussed above) or by selecting the create a new project option in the power calculator ?start project . a project name and project directory must be provided. after clicking continue , the power calculator main window will be displayed. however, in this case there are no resources added. the power estimation row for the routing resources is always available in the power calculator. users are then asked to add more information like the slice, ebr, i/o, pll and clock tree utilization to calculate the power consumption. for example, to add logic resources (as shown in figure 12-14), right-click on logic >> and then select add in the menu that pops up. figure 12-14. power calculator main window ?adding resources this adds a new row for the logic resource utilization with clock domain as clk_1. similarly, other resources like ebr, i/os, plls and routing can be added. each of these resources is for ac power estimation and categorized by clock domains.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-14 power calculator ?creating a new project with the ncd file if the post place and routed ncd ?e is available, the power calculator can use it to import the accurate information about the design data and resource utilization and calculate the power. when the power calculator is started, the ncd ?e is automatically placed in the ncd file option, if available in the project directory. otherwise, the user can browse to the ncd ?e in the power calculator. figure 12-15. power calculator start project window ?with post place and route ncd file the information from the ncd ?e is automatically inserted into the correct rows and the power calculator uses the clock names from the design, as shown in figure 12-16.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-15 figure 12-16. power calculator main window ?resource utilization picked up from the ncd file
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-16 power calculator ?open existing project the power calculator ?start project window also allows users to open an existing project. select the option open existing project and browse to the *.pep project ?e and click continue . this opens the existing project in similar windows as discussed above. this is shown in figure 12-17. figure 12-17. opening existing project in power calculator
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-17 power calculator ?total power the power calculator project created or opened using any of the methods discussed here would allow a user to calculate the power consumption for the device running with their design. the estimated power is indicated in the total section at the bottom of the table as shown in figure 12-18. figure 12-18. calculated power in the power calculator main window the second and third columns from the left indicate the dc (or static) and ac (or dynamic) power consumption. the total power consumption for the design can be seen in the same table. scroll down to the row labeled total . activity factor activity factor % (or af % ) is de?ed as the percentage of frequency (or time) that a signal is active or toggling of the output. most of the resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running. users are required to provide this value as a percentage under the af % column in the power calculator tool.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-18 another term used for i/os is the i/o toggle rate or the i/o toggle frequency. the af % is applicable to the pfu, routing and memory read write ports, etc. the activity of i/os is determined by the signals provided by the user (in the case of inputs) or as an output of the design (in the case of outputs). so, the rates at which i/os toggle de?e their activity. the toggle rate (or tr) in mhz of the output is de?ed as: toggle rate (mhz) = 1/2 * f max * af % users are required to provide the tr (mhz) value for the i/o instead of providing the frequency and af % in case of other resources. the af can be calculated for each routing resource, output or pfu, however it involves long calculations. the gen- eral recommendation of a design occupying roughly 30 % to 70 % of the device is that the af % used can be between 15 % to 25 % . this is an average value that can be seen most of the design. the accurate value of an af depends upon clock frequency, stimulus to the design and the ?al output. ambient and junction temperature and air?w a common method of characterizing a packaged devices thermal performance is with thermal resistance, . for a semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a given reference for each watt of power (heat) dissipated at the die surface. its units are ?/w. the most common examples are ja , thermal resistance junction-to-ambient (in ?/w) and jc , thermal resis- tance junction-to-case (also in ?/w). another factor is jb , thermal resistance junction-to-board (in ?/w). knowing the reference (i.e. ambient, case or board) temperature, the power, and the relevant value, the junction temperature can be calculated as per following equations. t j = t a + ja * p (1) t j = t c + jc * p (2) t j = t b + jb * p (3) where t j , t a, t c and t b are the junction, ambient, case (or package) and board temperatures (in ?) respectively. p is the total power dissipation of the device. ja is commonly used with natural and forced convection air-cooled systems. jc is useful when the package has a high conductivity case mounted directly to a pcb or heatsink. and jb applies when the board temperature adja- cent to the package is known. the power calculator utilizes the 25? junction temperature as its basis to calculate power, per equation 1 above. users can also provide the air?w values (in lfm) and ambient temperature to get a calculated value of the junc- tion temperature based on the power estimate. managing power consumption one of the most critical design factors today is reducing system power consumption, especially for modern hand- held devices and electronics. there are several design techniques that designers can use to signi?antly reduce overall system power consumption. some of these include: 1. reducing operating voltage. 2. operating within the speci?d package temperature limitations. 3. using optimum clock frequency reduces power consumption, as the dynamic power is directly proportional to the frequency of operation. designers must determine if a portion of their design can be clocked at a lower rate that will reduce power. 4. reducing the span of the design across the device. a more closely placed design utilizes fewer routing resources for less power consumption.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-19 5. reducing the voltage swing of the i/os where possible. 6. using optimum encoding where possible. for example, a 16-bit binary counter has, on average, only 12 % activity factor and a 7-bit binary counter has an average of 28 % activity factor. on the other hand, a 7-bit linear feedback shift register could toggle as much as 50 % activity factor, which causes higher power consumption. a gray code counter, where only one bit changes at each clock edge, will use the least amount of power, as the activity factor would be less than 10 % . 7. minimize the operating temperature, by the following methods: a. use packages that can better dissipate heat. for example, packages with lower thermal impedance. b. place heat sinks and thermal planes around the device on the pcb. c. better air?w techniques using mechanical air?w guides and fans (both system fans and device mounted fans). power calculator assumptions following are the assumptions made in the power calculator: 1. the power calculator tool is based on equations with constants based on room temperature of 25?. 2. the user can de?e the ambient temperature (ta) for device junction temperature (tj) calculation based on the power estimation. tj is calculated from user-entered ta and power calculation of typical room tem- perature. 3. the i/o power consumption is based on output loading of 5pf. users have ability to change this capacitive loading. 4. the current version of the power calculator allows users to get an estimate of the power dissipation and the current for each type of power supplies, that are v cc, v ccio, v ccj and v ccaux. for v ccaux, only static i ccaux values are provided in the calculator. additional v ccaux contributions due to differential output buffers, differential input buffers and reference input buffers must be added per pair for differential buffers or per pin for reference input buffers according to the user's design. see the equation given in this technical note for total dc power (i ccaux ). 5. the nominal v cc is used by default to calculate the power consumption. users can choose a lower or higher v cc from a list of available values. for example, the nominal v cc of 1.2v is used by default for the latticeecp/ec and latticexp families of devices. 6. the current versions also allows users to enter an air?w in linear feet per minute (lfm) along with the heat sink option to calculate the junction temperature. 7. the default value of the i/o types for the latticeec and latticexp devices is lvcmos12, 6ma. 8. the activity factor (af) is de?ed as the toggle rate of the registered output. for example, assuming that the input of a ?p-?p is changing at every clock cycle, 100 % af of a ?p-?p running at 100mhz is 50mhz.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-20 revision history technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com date version change summary june 2004 01.0 initial release. july 2004 01.1 provided additional description of the assumptions used in the power model. october 2004 01.2 updated screen shots for isplever 4.1. february 2005 02.0 added support for latticexp family throughout. added dc and ac power for a dedicated block like dsp for latticeecp devices. may 2005 02.1 updated the power supply sequencing and hot socketing section. updated the total dc power consumption to be sum of quiescent and the dc power of resources. november 2006 02.2 added calculation of i ccaux in power calculator equations section.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-21 appendix a. power calculator project example this example assumes that you have post place and route ncd netlist in the design folder. click on file > new or click on the new project button. the new project window will open as shown below. the various ?lds are ?led in automatically with the project name the same as the isplever project name and the directory also the same as the design folder. if the post place and route ncd ?e is available, the ncd file ?ld is also automatically ?led. users can also browse to the particular location to change the folder where they wish to create the power calculator project. users can also browse to the ncd ?e in case it is not available at the root design folder. click finish. this opens the main power calculator project window, as shown below. note that the project window above imports all the resource utilization information from the ncd ?e. it does not, however, include information such as the frequency at which the design is operating or the activity factors at which the various components are toggling. this information is to be ?led in by the user. the top portion of the power calculator window shows information such as the device family and device being con- sidered for power calculation, the v cc, which is by default the nominal v cc for the device, and operating conditions. operating conditions users can enter include the ambient temperature, and heat sink available. users can also select the air ?w values. there is a grayed box for junction temperature that shows tj based on the given conditions and the calculated power. if we assume the design is running at 100 mhz with a 10 % activity factor, the ?al power calculator will be as shown below.
estimating power using the power calculator lattice semiconductor for latticeecp/ec and latticexp devices 12-22
www.latticesemi.com 13-1 tn1082_01.4 february 2006 technical note tn1082 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. introduction the memory in the latticexp fpgas is built using flash cells, along with sram cells, so that con?uration memory can be loaded automatically at power-up, or at any time the user wishes to update the device. in addition to ?nstant-on capability, on-chip flash memory greatly increases design security by getting rid of the external con- ?uration bitstream; while maintaining the ease of use and reprogrammability of an sram-based fpga. while an external device is not required, the latticexp does support several external con?uration modes. the available external con?uration modes are: slave serial master serial slave parallel ispjtag (1149.1 interface) this guide will cover all the con?uration options available for the latticexp. programming overview the latticexp contains two types of memory, sram and flash (refer to figure 13-1). sram contains the fpga con?uration, essentially the ?uses that de?e the circuit connections; flash provides an internal storage space for the con?uration data. the sram can be con?ured using jtag, one of the external con?uration modes, or by using the data stored in on-chip flash. the con?uration process consists of sram initialization (clear the ram and the address pointers), loading the sram with the con?uration data, and setting the fpga into user mode (waking up the fpga). on-chip flash can be programmed by using jtag or by using the external slave parallel port. jtag flash pro- gramming can be performed any time the device is powered up. the slave parallel port uses the sysconfig pins and can program the flash directly or in the background. direct programming takes place during con? mode, background programming during user mode. the fpga enters con? mode at power up, when the programn pin is pulled low, or when a refresh command is issued via jtag; it enters user mode when it wakes up, i.e. when the device begins running user code. these two programming modes, direct and background, will be referred to in this document as flash direct and flash background. latticexp sysconfig usage guide
13-2 latticexp sysconfig lattice semiconductor usage guide figure 13-1. programming block diagram con?uration pins the latticexp supports two types of sysconfig pins, dedicated and dual-purpose. the dual-purpose pins are available as extra i/o pins if they are not used for con?uration. two con?uration mode pins, along with a programmable option, control the dual-purpose con?uration pins. the con?uration mode pins (cfg) are generally hard wired on the pcb and determine which con?uration mode will be used; the programmable option is accessed via preferences in lattice isplever design software, or as hdl source ?e attributes, and allows the user to protect the con?uration pins from accidental use by the user or the place-and-route software. the latticexp devices also support ispjtag for con?uration, including transparent readback, and for jtag testing. the following sections describe the functionality of the sysconfig and jtag pins. note that jtag and ispjtag will be used interchangeably in this document. table 13-1 is provided for reference. table 13-1. con?uration pins for the latticexp device pin name i/o type pin type mode used cfg[1:0] input, weak pull-up dedicated all programn input, weak pull-up dedicated all initn bi-directional open drain, weak pull-up dedicated all done bi-directional open drain with weak pull-up or active drive dedicated all cclk input or output dedicated all din input, weak pull-up dual-purpose serial dout/cson output dual-purpose serial or parallel csn input, weak pull-up dual-purpose parallel cs1n input, weak pull-up dual-purpose parallel writen input, weak pull-up dual-purpose parallel busy output, tri-state, weak pull-up dual-purpose parallel d[0:7] input or output dual-purpose parallel tdi input, weak pull-up jtag ispjtag 1149.1 tap sysconfig port flash memory space jtag 1532 master/slave serial slave parallel sram memory space port mode memory space program in seconds (sla v e parallel only) program in milliseconds program in microseconds sdm ,
13-3 latticexp sysconfig lattice semiconductor usage guide dedicated pins following is a description of the dedicated sysconfig pins for the latticexp device. these pins are used to con- trol or monitor the con?uration process. these pins are used for non-jtag programming sequences only. the jtag pins will be explained later in the ispjtag pins section of this document. cfg[1:0] the con?uration mode pins, cfg[1:0], are dedicated inputs with weak pull-ups. the cfg pins are used to select the con?uration mode for the latticexp, i.e. what type of device the latticexp will con?ure from. at power-on- reset (por), or when the programn pin is driven low, and depending on the con?uration mode selected, dif- ferent groups of dual-purpose pins will be used for device con?uration. table 13-2. latticexp con?uration modes when both cfg pins are high the device will con?ure itself by reading the data stored in on-chip flash; this is referred to as sdm, or self download mode. see the self-download section of this document for more information regarding sdm. programn the programn pin is a dedicated input with a weak pull-up. this pin is used to initiate a non-jtag sram con?- uration sequence. a high to low signal applied to programn sets the device into con?uration mode. the pro- gramn pin can be used to trigger con?uration at any time. if the device is using jtag then programn will be ignored until the device is released from jtag mode. if the cfg pins are not both high (not in sdm) then the con?uration sequence will proceed using the selected con?uration port. if both cfg pins are high (sdm), and the flash has been programmed, then the con?uration sequence will proceed using the data in on-chip flash. if both cfg pins are high (sdm), and the flash has not been programmed, the con?uration sequence will pause and wait for the flash done bit to be programmed. once the flash has been programmed, and programn is brought high, the con?uration sequence will continue. initn the initn pin is a dedicated bi-directional open drain pin with a weak pull-up. initn is capable of driving a low pulse out as well as detecting a low pulse driven in. during sram con?uration from an external device initn going low indicates that the sram is being initialized; initn going high indicates that the fpga is ready to accept con?uration data. to delay con?uration the initn pin can be held low externally. the device will not enter con?uration mode as long as the initn pin is held low. after con?uration has started initn is used to indicate a bitstream error. the initn pin will be driven low if the cal- tdo output jtag tck input with hysteresis jtag tms input, weak pull-up jtag note: weak pull-ups consist of a current source of 30ua to 150ua. the pull-ups for cfg and programn track v cc (core); the pull-ups for tdi and tms track v ccj ; all other pull-ups track the v ccio for that pin. con?uration mode cfg[1] cfg[0] slave serial 0 0 master serial 0 1 slave parallel 1 0 self download mode (sdm) 1 1 table 13-1. con?uration pins for the latticexp device (continued) pin name i/o type pin type mode used
13-4 latticexp sysconfig lattice semiconductor usage guide culated crc and the con?uration data crc do not match; done will then remain low and the latticexp will not wake up. during sram con?uration from on-chip flash initn is not used or monitored and is driven low. when programming on-chip flash the initn pin is only used to indicate an error during erase or program. if an error occurs initn will be driven low. during flash direct programming an error will prevent the fpga from con?- uring from the flash, during flash background programming an error will not affect the con?uration already run- ning in sram. done the done pin is a dedicated bi-directional open drain with a weak pull-up (default), or an actively driven pin. done will be driven low when the device is in con?uration mode and the internal done bit is not programmed. when the initn and programn pins go high (or in the case of sdm just programn goes high), and the inter- nal done bit is programmed, the done pin will be released (or driven high, if it is an actively driven pin). the done pin can be held low externally and, depending on the wake-up sequence selected, the device will not become functional until the done pin is externally brought high. reading the done bit is a good way for an external device to tell if the fpga is con?ured. when using jtag to con?ure sram the done pin is driven by the boundary scan cell, so the state of the done pin has no meaning during jtag con?uration. cclk cclk is a dedicated bi-directional pin; direction depends on whether a master or slave mode is selected. if a mas- ter mode is selected via the cfg pins, the cclk pin will become an output pin; otherwise cclk is an input pin. if the cclk pin becomes an output, the internal programmable oscillator is connected to the cclk and is driven out to slave devices. cclk will stop 100 to 500 clock cycles after the done pin is brought high and the device wake-up sequence completed. the extra clock cycles ensure that enough clocks are provided to wake-up other devices in the chain. when stopped, cclk becomes an input (tri-stated output). cclk will restart (become an out- put) on the next con?uration initialization sequence. the mcclk_freq parameter (see isplever software documentation) controls the cclk master frequency (see table 13-3). until changed during con?uration cclk will be 2.5 mhz. one of the ?st things loaded during con?- uration is the mcclk_freq parameter; once this parameter is loaded the frequency changes to the selected value using a glitchless switch. care should be exercised not to exceed the frequency speci?ation of the slave devices or the signal integrity capabilities of the pcb layout. table 13-3. master clock frequency selections cclk (mhz) cclk (mhz) cclk (mhz) 2.5 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 - 10.0 41 - note: default is the lowest frequency, 2.5 mhz.
13-5 latticexp sysconfig lattice semiconductor usage guide table 13-4. maximum con?uration bits table 13-5. sdm pin usage table 13-6. pins used for memory access programming sequence there are three types of programming, sram, flash direct, and flash background. this section goes through the process for each showing how the dedicated pins are used. sram: when not using sdm (self download mode, on-chip flash) to program sram the sequence begins when the internal power-on reset (por) is released or the programn pin is driven low (see figure 13-2). the lat- ticexp then drives initn low, tri-states the i/os, and initializes the internal sram and control logic. when this is density bitstream size (mb) lfxp3 1 lfxp6 1.6 lfxp10 2.8 lfxp15 4 lfxp20 4.9 con?uration mode sdm (self download mode) cfg[1:0] [1, 1] flash programming mode direct background direct background port sysconfig ispjtag 1 pins cclk, csn, cs1n, writen, d[0:7] tap user i/o states tristate user bscan user programn keep at high keep at high 2 busy status status not used initn pass/fail pass/fail not used 3 done done not used keep at high 4 persistent bit don? care on don? care 1. ispjtag can be used to program the flash regardless of the state of the cfg pins, however only if the device is in sdm can fl ash be used to con?ure sram 2. the state of the programn pin is ignored by the device during jtag flash programming but the pin should be held high as a low will inhibit flash to sram data transfer. 3. the state of the initn pin is ignored by the device during jtag flash programming but the pin should be allowed to ?at high using the internal pull-up. 4. the state of the done pin is ignored by the device during jtag flash programming but the pin should be allowed to ?at high u sing the internal pull-up as a low can keep the device from waking up. cfg pins cfg mode on-chip flash sram 1 0 write or read 2 write from readback 2, 3 x 1 x 1 jtag tap tap tap 1 1 sdm sysconfig on-chip flash sysconfig 1 0 slave parallel n/a 4 sysconfig sysconfig 0 1 master serial n/a 4 sysconfig n/a 5 0 0 slave serial n/a 4 sysconfig n/a 5 1. the ispjtag port is always available independent of the cfg setting. 2. readback can only be disabled by programming the security bit. 3. set the persistent bit to on to retain the sysconfig port for background readback. 4. flash access is not allowed in this mode. 5. sram readback is not allowed in this mode.
13-6 latticexp sysconfig lattice semiconductor usage guide complete, if programn is high, initn will be released. if initn is held low externally the latticexp will wait until it goes high. when initn goes high the latticexp begins looking for the con?uration data preamble on the selected con?uration port, as determined by the cfg pins. once con?uration is complete the internal done bit is set, the done pin goes high, and the fpga wakes up (enters user mode). if a crc error is detected when reading the bitstream initn will go low, the internal done bit will not be set, the done pin will stay low, and the latticexp will not wake up. when using sdm to program sram the sequence is similar but initn is not used or monitored (initn is driven low). the sequence begins when the internal power-on reset (por) is released or the programn pin is driven low (see figure 13-2). the latticexp then tri-states the i/os and initializes the internal sram and control logic. when initialization is complete the latticexp begins loading con?uration data from on-chip flash. as with non-sdm, once con?uration is complete the internal done bit is set, the done pin goes high, and the fpga wakes up (enters user mode). figure 13-2. sram con?uration timing diagram flash direct: flash direct programming is possible using the slave parallel port if both cfg pins are high (sdm). serial ports may not be used to program the flash. flash direct is only valid if the done pin is low (the sram is blank). the sequence begins when the programn pin is driven low. the latticexp tri-states the i/os, and initializes the internal sram and control logic. the latticexp waits for writen and both csn and cs1n pins to go low and then looks for the programming preamble followed by the erase, program, and verify commands. data is written and read on the d[0:7] pins. once the flash is programmed the programn pin can be brought high to start the transfer from flash to sram. flash background: flash background programming is possible using the slave parallel port if both cfg pins are high (sdm). serial ports may not be used to program the flash. flash background will not disturb the fpga's present con?uration. flash background programming may be used in both con? mode and user mode (done bit = 0 or 1). to support flash background programming in user mode the persistent bit must be set to on. when writen goes low, and csn and cs1n are low, the fpga will wait for the preamble and then look for the proper commands. a low on initn indicates an error during a flash erase or program. data is written and read on the d[0:7] pins. after programming the flash the user may toggle the programn pin to transfer the flash data to sram. initialize config u re w ake-up cclk program n i n it n do n e
13-7 latticexp sysconfig lattice semiconductor usage guide figure 13-3. flash programming timing diagram dual-purpose sysconfig pins the following is a list of the dual-purpose sysconfig pins. these pins are available as general purpose i/o after con?uration. if a dual-purpose pin is to be used both for con?uration and as a general purpose i/o the user must adhere to the following: the general purpose i/o (gpio) must maintain the same direction as it has during con?uration. in other words, if the pin is an input during con?uration it must remain an input as a gpio. if its an output during con?uration it must remain an output as a gpio. if its a bi-directional it must remain a bi-directional as a gpio. the i/o type must remain the same. in other words, if the pin is a 3.3v cmos pin (lvcmos33) during con?ura- tion it must remain a 3.3v cmos pin as a gpio. the persistent option must be set to off. the persistent option can be accessed by using the preference editor in isplever. the user is responsible for insuring that no internal or external logic will interfere with device con?uration. after con?uration these pins, if not used as gpio, are tri-stated and weakly pulled up. din din (data input) is a dual-purpose input with a weak pull-up. din is used for the serial bitstream con?urations. dout/cson the dout/cson is a dual-purpose output that is used in chain mode (daisy chaining). this pin can be used in serial or parallel modes and has two uses. for serial and parallel con?uration modes, when bypass chain mode is selected, this pin will become dout. in a serial con?uration mode, when the device becomes fully con?ured, a bypass instruction will be executed and the data on din will be presented on the dout pin through a bypass register. in this way the serial data is passed to the next device. in parallel con?uration mode the data will be serialized and then presented on dout; d[0] (msb) will be shifted out ?st followed by d[1], d[2] and so on to d[7] (lsb). for parallel con?uration mode, when flow_through chain mode is selected, this pin will become chip select out (cson). in flow_through chain mode, when the device is fully con?ured (the internal done bit goes d[0:7] i n it n program n w rite n cclk busy cs n cs1 n dri v e to lo w if error happens lo w to select direct programming. high to select backgro u nd programming. flash to sram u pload happens if do n e f u se is programmed and cfg[1:0] are high.
13-8 latticexp sysconfig lattice semiconductor usage guide high), the flow-through instruction will be executed and the cson pin will be driven low to enable the next devices chip select pin. the dout/cson bypass register will drive out a high upon power up and continue to do so until the execution of the bypass or flow-through instruction within the bitstream. chain mode is not supported when con?uring from internal flash (sdm). csn and cs1n both csn and cs1n are active low input pins with weak pull-ups and are used in parallel mode only. these inputs are or?d and used to enable the d[0:7] data pins to receive or output a byte of data. in non-sdm, when csn or cs1n are high, the d[0:7], initn, and busy pins are tri-stated. when both csn and cs1n are driven to a high value, they will reset the bypass/flow-through register. csn and cs1n are inter- changeable when controlling the d[0:7], initn, and busy pins. when sdm is selected and csn or cs1n are high, the d[0:7], initn, and busy pins are tri-stated. if the flash has not been programmed a high on both csn and cs1n will cause the latticexp to drive the initn pin low to reset the internal fpga con?uration circuitry. the latticexp will then monitor d[0:7] waiting for the con?uration preamble. csn and cs1n are interchangeable when controlling the d[0:7], initn, and busy pins. if sram or flash will need to be accessed while the device is in user mode (the done pin is high) then the per- sistent preference must be set to on in order to preserve these pins as csn and cs1n. writen the writen pin is an active low input with a weak pull-up and used for parallel mode only. the writen pin is used to determine the direction of the data pins d[0:7]. the writen pin must be driven low when a byte of data is to be clocked into the device and driven high when data is to be read from the device. if sram or flash will need to be accessed while the part is in user mode (the done pin is high) then the persis- tent preference must be set to on in order to preserve this pin as writen. busy in parallel mode the busy pin is a tri-stated output with a weak pull-up. the busy pin will be driven low by the lat- ticexp device only when it is ready to receive a byte of data from the d[0:7] pins or a byte of data is ready for read- ing. the busy pin can be used to support asynchronous peripheral mode (handshaking). this pin is used to indicate that the latticexp needs extra time to execute a command. if sram or flash will need to be accessed while the part is in user mode (the done pin is high) then the persis- tent preference must be set to on in order to preserve this pin as busy. d[0:7] the d[0:7] pins support slave parallel mode only. the d[0:7] pins are tri-statable bi-directional i/o pins used for data write and read. when the writen signal is low, and the csn and cs1n pins are low, the d[0:7] pins become data inputs. when the writen signal is driven high, and the csn and cs1n pins are low, the d[0:7] pins become data outputs. if either csn or cs1n is high d[0:7] will be tri-state. d[0] is the most signi?ant bit and d[7] is the least signi?ant bit. if sram or flash will need to be accessed while the part is in user mode (the done pin is high) then the persis- tent preference must be set to on in order to preserve these pins as d[0:7]. care must be exercised during read back of ebr or pfu memory. it is up to the user to ensure that reading these rams will not cause data corruption, i.e. these rams may not be read while being accessed by user code. ispjtag pins the ispjtag pins are standard ieee 1149.1 tap (test access port) pins. the ispjtag pins are dedicated pins and are always accessible when the latticexp device is powered up. when programming the sram via ispjtag the
13-9 latticexp sysconfig lattice semiconductor usage guide dedicated programming pins, such as done, cannot be used to determine programming progress. this is because the state of the boundary scan cell will drive the pin, per jtag 1149.1, rather than normal internal logic. tdo the test data output pin is used to shift out serial test instructions and data. when tdo is not being driven by the internal circuitry, the pin will be in a high impedance state. tdi the test data input pin is used to shift in serial test instructions and data. an internal pull-up resistor on the tdi pin is provided. the internal resistor is pulled up to v ccj. tms the test mode select pin controls test operations on the tap controller. on the falling edge of tck, depending on the state of tms, a transition will be made in the tap controller state machine. an internal pull-up resistor on the tms pin is provided. the internal resistor is pulled up to v ccj. tck the test clock pin, tck, provides the clock to run the tap controller, which loads and unloads the data and instruc- tion registers. tck can be stopped in either the high or low state and can be clocked at frequencies up to the fre- quency indicated in the device data sheet. the tck pin supports the value is shown in the dc parameter table of the data sheet. the tck pin does not have a pull-up. a pull-down on the pcb of 4.7 k is recommended to avoid inadvertent clocking of the tap controller as v cc ramps up. optional trst test reset, trst, in not supported on the latticexp device. vccj jtag v cc (v ccj ) supplies independent power to the jtag port to allow chaining with other jtag devices at a com- mon voltage. v ccj must be connected even if jtag is not used. this voltage may also power the jtag download cable. valid voltage levels are 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v. please see in-system programming design guidelines for ispjtag devices, available on the lattice web site at www .latticesemi.com , for further jtag chain information. con?uration and jtag voltage levels all of the control pins and programming pins default to lvcmos. cfg and programn are linked to v cc (core); tck, tdi, tdo, and tms track v ccj ; all other pins track the v ccio for that pin. con?uration modes and options the latticexp device supports several con?uration modes, utilizing serial or parallel data inputs, as well as self- con?uration. on power up, or upon driving the programn pin low, the cfg[1:0] pins are sampled to determine the mode that will be used to con?ure the latticexp device. the cfg pins are generally hard wired on the pcb and determine which port the device will use to retrieve its con?uration data. config_mode is a programmable option accessed via preferences in lattice isplever design software, or as hdl source ?e attributes, and allow the user to protect the con?uration pins from accidental use by the user or the place-and-route software. table 13-7 shows the mode, cfg[1:0], and the software config_mode parameter. the following sections break- down each con?uration mode.
13-10 latticexp sysconfig lattice semiconductor usage guide table 13-7. con?uration modes for the latticexp con?uration options several con?uration options are available for each config_mode. when daisy chaining multiple fpga devices a con?uration over?w option is provided. con?uration data over- ?w occurs once the ?st fpga has completed its download, the remaining data in the con?uration storage device is then output through the ?st fpga to subsequent fpgas. con?uration data over?w is not supported when using sdm. when using a master clock, the master clock frequency can be set. a security bit is provided to prevent sram or flash readback. by setting the proper parameters in the lattice isplever design software the selected con?uration options are set in the generated bitstream. as the bitstream is loaded into the device the selected con?uration options take effect. these options are described in the following sections. bypass over?w option the bypass over?w option can be used in serial and parallel device daisy chains. when the ?st device has com- pleted con?uration data download, and the bypass option preference is selected, data coming into the device con?uration port on the sysconfig pins will over?w serially out of dout and into the din pin of the next slave serial device. the bypass option is selected in isplever by right-clicking on generate bitstream data and clicking on properties. in serial con?uration mode, once all of the con?uration data has been loaded into the ?st device, the bypass option connects the din pin to dout pin via a bypass register. the bypass register is initialized with a ? at the beginning of con?uration. in parallel con?uration mode, once all of the con?uration data has been loaded into the ?st device, the bypass option causes the data coming from d[0:7] to be serially shifted to dout. the serialized data is shifted to dout through the bypass register. d[0] of the byte wide data will be shifted out ?st followed by d[1], d[2] and so on. once the bypass option starts, the device will remain in bypass until the wake up sequence completes. the bypass option can be aborted by setting both csn and cs1n high. flow-though over?w option the flow-through over?w option is used in parallel mode only. the flow-through option causes the cson pin to go low when the fpga has received all of its con?uration data, driving the chip select on the next device in the con?uration mode cfg[1] cfg[0] config_mode 1 chain mode 2 slave serial (no overload option) 0 0 slave_serial disable slave serial (bypass on) 0 0 slave_serial bypass master serial (no overload option) 0 1 master_serial disable master serial (bypass on) 0 1 master_serial bypass slave parallel (no overload option) 1 0 slave_parallel disable slave parallel (bypass on) 1 0 slave_parallel bypass slave parallel (flow through on) 1 0 slave_parallel flowthrough self download mode (sdm) 1 1 none/slave_parallel 4 disable ispjtag (1149.1 interface) x 3 x 3 none 5 1. config_mode can be found in the isplever preference editor. 2. chain_mode can be found in the isplever bitgen options (right-click on generate bitstream data and click on properties). 3. the ispjtag interface is always on. 4. if ispjtag is used exclusively to access the on-chip flash and sram select none, if slave parallel is used to access the flas h and/or the sram select slave_parallel. 5. the none selection indicates that no dual-purpose pins are reserved for con?uration. this is the default.
13-11 latticexp sysconfig lattice semiconductor usage guide daisy chain so that it will start reading con?uration data from d[0:7]. the flow through option will also tri-state the d[0:7], initn, and busy pins, once all of the con?uration data has been received, in order to prevent interference with other devices in the daisy chain. once the flow-through option starts, the device will remain in flow-through until the wake up sequence com- pletes. the flow-through option can be aborted by setting both csn and cs1n high. master clock if the cfg pins indicate that this is a master device the cclk pin will become an output with the frequency set by the user. the default master clock frequency is 2.5 mhz. the user can determine the master clock frequency by setting the mcclk_freq preference in the lattice isplever design software. one of the ?st things loaded during con?uration is the mcclk_freq parameter; once this parameter is loaded the frequency changes to the selected value using a glitchless switch. care should be exercised not to exceed the frequency speci?ation of the slave devices or the signal integrity capabilities of the pcb layout. see table 13-3 for available options. security bit setting the security bit prevents readback of the sram and flash from jtag or the sysconfig pins. when the security bit is set the only operations available are erase and write. the security bit is updated as the last operation of sram con?uration or flash programming. by using on-chip flash, and setting the security bit, the user can create a very secure device. the security bit is accessed via the preference editor in isplever design software. more information on device security can be found in the document fpga design security issues: using the ispxpga family of fpgas to achieve high design security, available on the lattice semiconductor web site at www .latticesemi.com . slave serial mode the cclk pin becomes an input and data at di is clocked on the rising edge of cclk. after the device is fully con- ?ured, if the bypass option has been set, data sent to di will be presented to the next device via the dout pin as shown in figure 13-4. master serial mode in master serial mode the device will drive cclk out to the slave serial devices in the chain and the serial prom that will provide the bitstream. the master device accepts the data at din on the rising edge of cclk. the master serial device starts driving cclk at the beginning of the con?uration and continues to drive cclk until the exter- nal done pin is driven high and an additional 100 to 500 clock cycles have been generated. the cclk frequency on power up defaults to 2.5 mhz. the master clock frequency default remains unless a new clock frequency is loaded from the bitstream. if a master serial device is daisy chained with slave serial devices the bypass option should be used so that over- ?w con?uration data is directed to the dout pin. con?uration mode cfg[1] cfg[0] config_mode chain mode slave serial (no overload option) 0 0 slave_serial disable slave serial (bypass on) 0 0 slave_serial bypass con?uration mode cfg[1] cfg[0] config_mode chain mode master serial (no overload option) 0 1 master_serial disable master serial (bypass on) 0 1 master_serial bypass
13-12 latticexp sysconfig lattice semiconductor usage guide figure 13-4 shows a serial daisy chain. the daisy chain allows multiple lattice fpga devices to be con?ured using one con?uration storage device. the center device operates in master serial with the bypass option set while the other lattice fpga devices in the daisy chain operate in slave serial mode. the reset/oe pin of the prom is driven by initn while the chip select pin is driven by the done pin of the devices. figure 13-4. master and slave serial daisy chain slave parallel mode in slave parallel mode a host system sends the con?uration data in a byte-wide stream to the device. the cclk, csn, cs1n, and writen pins are driven by the host system. the slave parallel con?uration mode allows multi- ple devices to be chained in parallel, as shown in figure 13-5. writen, csn, and cs1n must be held low to write to the device; data is input from d[0:7]. slave parallel mode can also be used for readback of the internal con?uration. by driving the writen pin low, and csn and cs1n low, the device will input the readback instructions on the d[0:7] pins; writen is then driven high and data read on d[0:7]. in order to support readback the persistent bit in isplevers preference editor must be set to on. the slave parallel mode can support two types of over?w, bypass and flow-through. if the bypass option is set, after the ?st device has received all of its con?uration data, the data presented to the d[0:7] pins will be serialized and bypassed to the dout pin. if the flow-through option is set, after the ?st device has received all of its con?- uration data, the cson signal will drive the following parallel mode devices chip select low as shown in figure 13- 5. to support asynchronous con?uration, where the host may provide data faster than the fpga can accept it, slave parallel mode can use the busy signal. by driving the busy signal high the slave parallel device tells the host to pause sending data. see figure 13-6. con?uration mode cfg[1] cfg[0] config_mode chain mode slave parallel (no overload option) 1 0 slave_parallel disable slave parallel (bypass on) 1 0 slave_parallel bypass slave parallel (flow through on) 1 0 slave_parallel flowthrough latticexp master serial cclk program n i n it n do n e di n dout dout cfg0 cfg1 latticexp sla v e serial cclk program n i n it n do n e di n cfg1 cfg0 master program serial prom data clk reset/oe cs
13-13 latticexp sysconfig lattice semiconductor usage guide figure 13-5. master and slave parallel daisy chain figure 13-6. asynchronous usage of slave parallel con?uration mode latticeec master parallel cclk program n i n it n do n e d[0:7] cfg2 cfg1 cfg0 cs1 n w rite n cs0 n serial prom data[0:7] clk reset/oe cs latticexp sla v e parallel cclk program n i n it n do n e d[0:7] cfg1 cfg0 cs1 n w rite n cs n csout n master program *1 *2 cs n bypass reset *1,2 *1 both cs pins can b e held or dri v en lo w *2 an option that allo w s the bypass and flo w -thro u gh option to b e reset latticexp sla v e parallel (asynchrono u s) cclk program n i n it n do n e d[0:7] cfg1 cfg0 cs1 n w rite n cs n dout dout busy latticexp sla v e serial cclk program n i n it n do n e di n cfg1 cfg0 *1 *1,2 *2 cs n bypass reset data[0:7] i n it do n e clock program w rite busy *1 both cs pins can b e held or dri v en lo w *2 an option that allo w s the bypass and flo w -thro u gh option to b e reset
13-14 latticexp sysconfig lattice semiconductor usage guide figure 13-6 shows an asynchronous peripheral write sequence using the bypass option. to send con?uration data to a device, the writen signal has to be asserted. during the write cycle, the busy signal provides hand- shaking between the host system and the latticexp device. when busy is low the device is ready to read a byte of data at the next rising edge of cclk. the busy signal is set high when the device reads the data and the device requires extra clock cycles to process the data. the csn or cs1n signal can be used to temporarily stop the write process by setting either to a high state if the host system is busy. the latticexp device will resume con?uration when the both csn and cs1n signals are set low again. if either over?w option is selected, both the csn and cs1n pins can be set high to reset the slave parallel device out of the over?w option. self download mode self download mode (sdm) allows the fpga to con?ure itself without using any external devices, and because the bitstream is not exposed this is also a very secure con?uration mode. the user may access on-chip flash using ispjtag or the slave parallel port on the sysconfig pins. jtag may access the on-chip flash any time the device is powered up, without disturbing device operation. jtag may also read and write the con?uration sram. if access to the on-chip flash and sram is limited to jtag then config_mode should be set to none, freeing the dual-purpose pins for use as general purpose i/o. the slave parallel port can also be used to access on-chip flash. if the slave parallel port is used then config_mode should be set to slave_parallel. writen, csn, and cs1n must be held low to write to on-chip flash; data is input from d[0:7]. the slave parallel port can also be used for readback of both flash and sram. by driving the writen pin low, and csn and cs1n low, the device will input the readback instructions on the d[0:7] pins; a bit in the read command will determine if the read is directed to flash or sram. in order to support read- back while the device is in user mode (the done pin is high) the persistent bit in isplevers preference edi- tor must be set to on. sdm does not support over?w. ispjtag mode the latticexp device can be con?ured through the ispjtag port. the ispjtag port is always on and available, regardless of the con?uration mode selected. a config_mode of none can be selected in the lattice isplever design software to tell the place and route tools that the jtag port will be used exclusively, i.e. the serial and parallel ports will not be used. setting the config_mode to none allows software to use all of the dual-pur- pose pins as general purpose i/os. isc 1532 con?uration through the ispjtag port conforms to the ieee 1532 standard. the boundary scan cells take con- trol of the i/os during any 1532 mode instruction. the boundary scan cells can be set to a pre-determined value whenever using the jtag 1532 mode. because of this the dedicated pins, such as done, cannot be relied upon for valid con?uration status. con?uration mode cfg[1] cfg[0] config_mode chain mode self download mode (sdm) 1 1 none/slave_parallel disable con?uration mode cfg[1] cfg[0] config_mode chain mode ispjtag (1149.1 interface) x x none
13-15 latticexp sysconfig lattice semiconductor usage guide transparent readback the ispjtag transparent readback mode allows the user to read the content of the device sram or flash while the device remains in a functional state. care must be exercised when reading ebr and distributed ram, as it is possible to cause con?cts with accesses from the user design (causing possible data corruption). the i/o and non-jtag con?uration pins remain active during a transparent readback. the device enters the transparent readback mode through a jtag instruction. boundary scan and bsdl files bsdl ?es for this device can be found on the lattice web site at www .latticesemi.com . the boundary scan ring covers all of the i/o pins, as well as the dedicated and dual-purpose sysconfig pins. power save mode an i/o power save mode option is available for the latticexp device and will deactivate portions of the i/o cell driv- ers. this is only valid when using comparator type inputs pins (pins that use vref), like hstl, sstl, etc. power save mode limits some of the functionality of boundary scan. for boundary scan testing it is recommended that the i/o power save mode be set to off so that all of the i/os will be fully functional. wake up options when con?uration is complete (the sram has been loaded), the device should wake up in a predictable fashion. the following selections determine how the device will wake up. two synchronous wake up processes are avail- able. one automatically wakes the device up when the internal done bit is set regardless of whether the done pin is held low externally or not, the other waits for the done pin to be driven high before starting the wake up process. the done_ex preference determines whether the external done pin will control the synchronous wake up. wake up sequence table 13-8 provides a list of the wake up sequences supported by the latticexp. table 13-8. wake up sequences supported by latticexp sequence phase t0 phase t1 phase t2 phase t3 1 done goe, gwdis, gsr 2 done goe, gwdis, gsr 3 done goe, gwdis, gsr 4 done goe gwdis, gsr 5 done goe gwdis, gsr 6 done goe gwdis gsr 7 done goe gsr gwdis 8 done goe, gwdis, gsr 9 done goe, gwdis, gsr 10 done gwdis, gsr goe 11 done goe gwdis, gsr 12 done goe, gwdis, gsr 13 goe, gwdis, gsr done 14 goe done gwdis, gsr 15 goe, gwdis done gsr 16 gwdis done goe, gsr 17 gwdis, gsr done goe 18 goe, gsr done gwdis 19 goe, gwdis, gsr done 20 goe, gwdis, gsr done
13-16 latticexp sysconfig lattice semiconductor usage guide figure 13-7. wake up sequence to internal clock synchronous to internal done bit if the latticexp device is the only device in the chain, or the last device in a chain, the wake up process should be initiated by the completion of the con?uration. once the con?uration is complete, the internal done bit will be set and then the wake up process will begin. synchronous to external done signal the done pin can be selected to delay wake up. if done_ex is true then the wake up sequence will be delayed until the done pin is high. the device will then follow the wake_up sequence selected. wake up clock selection the wake_up sequence is synchronized to a clock source. the user selects the clock source to wake up to. the clock sources are cclk, tck, and user clock. the default can be either tck or cclk, depending on the pro- gramming/con?uration method selected. the default clock will be tck if using ispjtag and cclk if using sysconfig. the user clock is chosen in the users design. the user can select any of the clk pins of the device, or a net (routing node), as the user clock source. figure 13-7 uses bclk to represent the user clock. the wakeup_clk defaults to tck or cclk. software selectable options in order to control the con?uration of the latticexp device beyond the default settings, software preferences are used. table 13-9 is a list of the preferences with their default settings. 21 (default) goe gwdis, gsr done 22 goe, gwdis gsr done 23 gwdis goe, gsr done 24 gwdis, gsr goe done 25 goe, gsr gwdis done table 13-8. wake up sequences supported by latticexp (continued) sequence phase t0 phase t1 phase t2 phase t3 bclk do n e bit global output e n able global set/reset global w rite disable do n e pi n t0 t1 t2 t3
13-17 latticexp sysconfig lattice semiconductor usage guide table 13-9. software preference list for the latticexp persistent in order to use the sysconfig port while in user mode to read sram or flash memory, the persistent prefer- ence must be set to on. persistent = on preserves all of the sysconfig pins so the fpga can be accessed by an external device at any time. persistent = on lets the software know that all of the dual-purpose con?u- ration pins are reserved and not available for use by the ?ter or the user. persistent = on reserves all of the dual-purpose sysconfig pins, without regard to config_mode. con?uration mode the device knows which physical sysconfig port will be used by reading the state of the cfg[1:0] pins, but the ?ter software also needs to know which port will be used. the ?ter cannot sample the con?uration pins so the user must tell the ?ter by selecting the proper config_mode. config_mode tells the ?ter which sysconfig pins are not available for use as user i/o. there are several additional con?uration options, such as over?w, that are set by software. these options are selected by clicking properties under generate bitstream data in isplever. if either over?w option is selected, then the done_ex and wake_up selections will be set to correspond (see table 13-10). refer to the con?ura- tion modes and options section of this document for more details. table 13-10. over?w option defaults done open drain the ?one_od preference allows the user to con?ure the done pin as an open drain pin. the ?one_od preference is only used for the done pin. when the done pin is driven low, internally or externally, this indicates that con?uration is not complete and the device is not ready for the wake up sequence. once con?uration is complete, with no errors, and the device is ready for wake up, the done pin must be driven high. for other devices to be able to control the wake up process an open drain con?uration is needed to avoid contention on the done pin. the ?one_od preference for the done pin defaults to on. the done_od preference is automatically set to on if the done_ex preference is set to on. see table 13-11 for more information on the relationship between done_od and done_ex. preference name default setting [list of all settings] persistent off [off, on] config_mode none[slave_parallel, slave_serial, master_serial, none] done_od on [off, on] done_ex off [off, on] mcclk_freq lowest frequency (see table 13-3) config_secure off [off, on] wake_up 21 (done_ex = off) 4 (done_ex = on) wakeup_clk external [external, user] pwrsave off [off, on] over?w option done_ex preference wake_up preference off off (default) default 21 (user selectable 1 through 25) off on default 21 (user selectable 1 through 25) on (either) on (automatically set by software) default 4 (user selectable 1 through 7)
13-18 latticexp sysconfig lattice semiconductor usage guide done external the latticexp device can wake up on its own after the done bit is set or wait for the done pin to be driven high externally. set done_ex = on to delay wake up until the done pin is driven high by an external signal synchro- nous to the clock; select off to synchronously wake up when the internal done bit is set and ignore any external driving of the done pin. the default is done_ex = off. if done_ex is set to on, done_od will be set to on. if an external signal is driving the done pin it should be open drain as well (an external pull-up resistor may need to be added). see table 13-11 for more information on the relationship between done_od and done_ex. table 13-11. summary of done pin preferences (preferences) master clock selection when the user has determined that the latticexp will be a master con?uration device (by properly setting the cfg[1:0] pins), and therefore provide the source clocking for con?uration, the cclk pin becomes an output with the frequency set by the value in mcclk_freq. at the start of con?uration the device operates at the default master clock frequency of 2.5 mhz. some of the ?st bits in the con?uration bitstream are mcclk_freq, once these are read the clock immediately starts operating at the user-de?ed frequency. the clock frequency is changed using a glitchless switch. security when config_secure is set to on, no read back operation will be supported through the sysconfig or ispjtag port of the general contents. the ispjtag deviceid area is readable and not considered securable. default is off. wake up sequence the wake_up sequence controls three internal signals and the done pin. the done pin will be driven after con- ?uration and prior to user mode. see the wake up sequence section of this document for an example of the phase controls and information on the wake up selections. the default setting for the wake_up preference is determined by the done_ex setting. wake up with done_ex = off (default setting) the wake_up preference for done_ex = off (default) supports the user selectable options 1 through 25, as shown in table 13-8. if the user does not select a wake-up sequence, the default, for done_ex = off, will be wake-up sequence 21. wake up with done_ex = on the wake_up preference for done_ex = on supports the user selectable options 1 through 7, as shown in table 13-8. if the user does not select a wake-up sequence, the default will be wake-up sequence 4. wake up clock selection the wake_up sequence is synchronized to a clock source. the user can select the clock source to wake up to. the clock sources are either external (cclk or tck) or user clock. the default is external and can be either tck or cclk, depending on the programming/con?uration method selected. the default clock will be tck if using ispjtag and cclk if using sysconfig. the user clock is chosen in the users design. the user can select any of the clk pins of the device, or a net (routing node), as the user clock source. wakeup_clk defaults to tck or cclk. power save the i/o power save option will deactivate portions of the i/o cell drivers. this is only valid when using comparator type inputs pins (pins that use vref), like hstl, sstl, etc. done_ex wake up process done_od off external done ignored user selected on external done low delays set to default (on)
13-19 latticexp sysconfig lattice semiconductor usage guide power save mode limits some of the functionality of boundary scan. for boundary scan testing it is recommended that the i/o power save mode be set to off so that all of the i/os will be fully functional. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
www.latticesemi.com 14-1 tn1054_01.2 february 2006 technical note tn1054 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. introduction this document describes the functionality and usage of isptracy, lattices integrated logic analyzer for the ispxpga , latticesc, latticeecp2, latticeecp, latticeec and latticexp fpga families. the isp- tracy tool consists of an intellectual property (ip) hardware block and three software tools ?core generator, core linker and ispla. isptracy allows for fast debugging and functional veri?ation inside lattice fpga devices without the need for expensive test and measurement equipment. debugging is accomplished through the hard- ware ip compiled in the design, on device block ram and the device jtag port. isptracy ip core features the isptracy ip core is highly con?urable. these con?urable features include width and depth of data capture lines, multiple edge and level sensitive trigger signals, complex comparison for trigger events, delayed trigger events and more. isptracy allows multiple isptracy ip cores to be included in a single design. the following table summarizes the features of the isptracy ip core. table 14-1. isptracy ip core features isptracy ip module generator to include isptracy cores in a design, the ?st step is to run ipexpress from the isplever project navigator. figure 14-1 shows the launch button for the ip manager program. figure 14-1. ipexpress launch button in isplever project navigator feature description depth of memory capture 256 to 4096 samples data capture width 8 to 256 bits triggering schemes rising/falling edges, level logic, comparison, trigger after combination of events number of triggers 4 to 128 bits, can be a combination of edge and level sensitive signals number of core up to 16 isptracy cores lattice isptracy usage guide
14-2 lattice semiconductor lattice isptracy usage guide once ipexpress is launched, you will be presented with the option of generating the isptracy ip module by selecting the jtag module uner architecture and clicking the customize button. figure 14-2 shows the ipexpress window. selections for the project path and module name are made through this window figure 14-2. isptracy ip manager program window isptracy core generator the isptracy core generator under jtag module provides all the controls for customizing the isptracy core(s). selections on this page in?ence the ?al size of the core(s) inside the fpga and features available in terms of triggers, size of data bus and depth of memory capture. figure 14-3 shows the core generator window and table 14-3 contains descriptions of each of the ?ures available in the ip core. once the core features are selected, clicking on the generate button will create the necessary ?es for the core linker program. figure 14-3. isptracy core generator window
14-3 lattice semiconductor lattice isptracy usage guide table 14-2. isptracy core generator features and descriptions feature description number of core the number of ispla(s) in an xpga can be either 1, 2, 3, ..., or 16. the ispla needs to be con?ured before use. after [generate] button is clicked, the isptracy software will gen- erate the required logic for each ispla based on its own con?uration. isptracy core lists the ispla. size comparison logic the comparison logic can compare the trigger bus with the patterns setting by the user. this ?ld needs to be on for ">", ">=", "<", "<=" comparison. if it's off, only = (equal) and <> (not equal) comparison can be preformed. event counter size this ?ld con?ures the size of the event counter. if this ?ld is 8, the counter can be set to the value from 1 to 255. if this ?ld is 16, the counter can be set to the value from 1 to 65535. if this ?ld is "none", the counter logic is removed (i.e. counter value n always equal 1). if the counter value is set to n, then when the pattern occurs n times, the corre- sponding event will be true. trigger same as trace if this is on, the trace bus and trigger bus are the same bus. if this is off, the trace bus and trigger bus are different and they can have different bus sizes. trigger bus size this speci?s the trigger bus size. it can be 4, 5, 6, ..., up to 128. trace bus size this speci?s the trace bus size. it can be a multiple of 8 up to 256 (i.e. 8, 16, 24, 32, 40,..., up to 256). trace memory depth this is the depth of the trace memory. it de?es the number of trace bus samples that ispla can capture. this ?ld can be set be set to 512, 1024, 2048, or 4096. it can also be set to 256 if the trace bus size is a multiple of 16 (i.e. 16, 32, 48, etc.). sample_after_trigger mode logic the ?ld causes the sample_after_trigger mode logic to be removed or not. if this is on, the trace mode can be set to "one shot" mode or "sample after trigger" mode. if this is off, the trace can only be running at "one shot" mode. when this logic is turned off, the ispla will use less logic. number of edge trigger signals the trigger bus signals can be either edge sensitive signals or level sensitive signals. the level sensitive trigger signals can only be set to 0, 1 or x (don't care). the edge sensitive trigger signals can be set to 0, 1, x, r (rising edge), f (falling edge) or b (both edges). this ?ld speci?s the number of edge sensitive trigger signals. number of level trigger signals this ?ld speci?s the number of level sensitive trigger signals. note that (number of edge trigger signals) + (number of level trigger signals) = (trigger bus size). trigger input logic this speci?s if the "trigger input" logic exists. if this ?ld is "none", the logic will be removed and the trigger condition can only be set using ev0 and ev1. if this ?ld is set to "pin" the trigger input logic exists and the trigger input should come from an ispxpga device i/o pin. the trigger input can be set to either active low or active high. trigger output logic this speci?s if the "trigger output" logic exists. if this ?ld is "none", the logic will be removed. if this ?ld is set to "pin" the trigger output logic exists and the trigger output should go out through an xpga device i/o pin. if this is set to "ispla", the trigger output will be connected to the trigger input of other isplas. you must choose "trigger input logic" of the other isplas to be this ispla. same as the trigger input, the trigger output can be set to either active low or active high. at least one ispla should have this option set to "pin." generate generates the core. cancel cancels the action and closes the dialog box without saving any changes. help displays online help topics for this dialog box.
14-4 lattice semiconductor lattice isptracy usage guide isptracy core linker once the isptracy core is created, it must be linked into the target design. this is accomplished through the core linker program. the core linker program allows the user access to internal and external signals of the target design. the internal signals can be named signals or component ports. this window also displays the available isp- tracy ports. to connect isptracy signals, the desired signal(s) are selected in the left-hand signal window. sig- nals chosen from this window are re?cted in the selected signals window. signals must be highlighted in this window, the isptracy port window and then click on the connect button to connect the signals in the rtl code. multiple instances (for example, a data bus) can be connected at once by highlighting the ?st signal, holding down the shift key and clicking on the last desired signal. figure 14-4 shows the isptracy core linker window. figure 14-4. isptracy core linker program window when you click the save button (or file -> save menu selection), the core linker will create modi?d versions of your source ?e, with the isptracy core linked into these modi?d ?es. only design ?es that are directly con- nected to the core will be modi?d. a dialogue box will indicate which ?es have been changed and will need to be replaced in the design project for isptracy to function. the design ?es names will be the original ?es names with the module name for the isptracy core (from the ipexpress isptracy core generation) appended. figure 14-5 shows the changed ?es dialogue box.
14-5 lattice semiconductor lattice isptracy usage guide figure 14-5. isptracy core linker output window after clicking ok, you will be back in the isptracy core linker. you may now close this and return to the isplever project navigator. at this point, it is necessary to replace the original design ?es with the isptracy core linker modi?d ?es. figure 6 shows this ?e replacement process on a design. figure 14-6. original project navigator (left) and isptracy project navigator (right)
14-6 lattice semiconductor lattice isptracy usage guide isptracy ispla program after replacing the original design ?es with the isptracy core linker modi?d ?es, it is necessary to re-compile the design and then program the device using the ispvm software (see online documentation for running the ispvm program). once the device is successfully programmed, the ispla program needs to be started. figure 14- 7 shows the ispla launch button from the project navigator. figure 14-7. ispla launch button in isplever project navigator ispla provides for capture and display of data from the isptracy core. the program is used to setup the trigger events counters, trigger location in data buffer, event patterns, event comparisons and data display. figure 14-8 shows the initial startup windows required to run ispla. figure 14-8. ispla program window ?new project setup once the project is set up, you can open up a trigger setup and viewing window for the project by clicking on window -> show ispla window -> device 0 -> device 0 la0. figure 9 shows the ispla window. there are three tabs available under this window, trigger setup, event pattern and signal analysis (data view).
14-7 lattice semiconductor lattice isptracy usage guide figure 14-9. ispla project setup window - trigger setup options the options available in the trigger setup window are based on selected isptracy core options. in the trace mode box, one shot mode will always be available, but sample after trigger availability is dependent on selecting sample_after_trigger mode logic => on. the position slider can be used to select the trigger point anywhere within the data memory depth. there are three precon?ured trigger positions in the drop-down menu box. they are pre-trigger (5 % before and 95 % after trigger), center (50 % before and 50 % after trigger) and post trigger (95 % before and 5 % after trigger). in the compare mode box the options are also dependant on core con?uration. ev0 and ev1 are always available. the comparisons available and number of samples will be determined by the size comparison logic and event counter size. the equal to comparison is always available. additions compari- sons include >, <. !=, <=, >=. the trigger condition box con?ures which event or combination of events will cause the ispla program to trigger and upload captured data from the device. in a simple case, this would be set to wait for ev0. more complex cases could possible be wait for ev0 and ev1, or after ev1 wait until ev0. the ?al two boxed on this screen control the signal polarity of trigger in (if available) and trigger out.
14-8 lattice semiconductor lattice isptracy usage guide figure 14-10. ispla project setup window - event pattern setup the event pattern window con?ures the patterns for ev0 and ev1. pattern 0 corresponds to ev0 and pattern 1 corresponds to ev1. the sample types for trigger signals depends on whether the signal is edge or level sensitive. if the signal is level sensitive, in the middle pattern window, only logic 0 (0) ,logic (1) or don't care (x) are available. for edge sensitive signals, the options are logic 0 (0), logic 1 (1), rising (r), falling (f), both/either edge (b) or don't care (x). in this window, changes to the pattern are made in the center section (pattern 1 or pattern 0) and the changes are re?cted in the right section. to begin sampling , click on the green run button. sampling will complete when the trigger conditions are met. the data will be uploaded through the jtag cable and results displayed i the signal analysis window. figure 14-11 shows the signal analysis window after a data capture cycle. figure 14-11. ispla signal analysis window
14-9 lattice semiconductor lattice isptracy usage guide conclusion isptracy is a full-featured logic analysis tool for use in lattice fpga products including ispxpga, latticeecp/ec and latticexp families. using internal device resources, including pff/pfu, embedded block ram and the device jtag port, the user can quickly verify functionality and assist in device debugging. isptracy reduces the need for external test and measurement equipment to debug fpga projects, while providing full access to a wide range of internal signals, components and design elements. references isptracy usage guide, 2/07/04 rev. 0.1, page 14 of 14. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
www.latticesemi.com 16-1 tn1008_02.1 october 2005 technical note tn1008 introduction coding style plays an important role in utilizing fpga resources. although many popular synthesis tools have sig- ni?antly improved optimization algorithms for fpgas, it still is the responsibility of the user to generate meaningful and ef?ient hdl code to guide their synthesis tools to achieve the best result for a speci? architecture. this appli- cation note is intended to help designers establish useful hdl coding styles for lattice semiconductor fpga devices. it includes vhdl and verilog design guidelines for both novice and experienced users. the application note is divided into two sections. the general coding styles for fpgas section provides an over- view for effective fpga designs. the following topics are discussed in detail: hierarchical coding design partitioning encoding methodologies for state machines coding styles for finite state machines (fsm) using pipelines comparing if statements and case statements avoiding non-intentional latches the hdl design with lattice semiconductor fpga devices section covers speci? coding techniques and exam- ples: using the lattice semiconductor fpga synthesis library implementation of multiplexers creating clock dividers register control signals (ce, lsr, gsr) using pic features implementation of memories preventing logic replication and fanout comparing synthesis results and place and route results general coding styles for fpga the following recommendations for common hdl coding styles will help users generate robust and reliable fpga designs. hierarchical coding hdl designs can either be synthesized as a ?t module or as many small hierarchical modules. each methodology has its advantages and disadvantages. since designs in smaller blocks are easier to keep track of, it is preferred to apply hierarchical structure to large and complex fpga designs. hierarchical coding methodology allows a group of engineers to work on one design at the same time. it speeds up design compilation, makes changing the imple- mentation of key blocks easier, and reduces the design period by allowing the re-use of design modules for current and future designs. in addition, it produces designs that are easier to understand. however, if the design mapping into the fpga is not optimal across hierarchical boundaries, it will lead to lower device utilization and design perfor- mance. this disadvantage can be overcome with careful design considerations when choosing the design hierar- chy. here are some tips for building hierarchical structures: the top level should only contain instantiation statements to call all major blocks any i/o instantiations should be at the top level any signals going into or out of the devices should be declared as input, output or bi-directional pins at the top level hdl synthesis coding guidelines for lattice semiconductor fpgas
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-2 memory blocks should be kept separate from other code design partitioning by effectively partitioning the design, a designer can reduce overall run time and improve synthesis results. here are some recommendations for design partitioning. maintain synchronous sub-blocks by registering all outputs it is suggested to arrange the design boundary such that the outputs in each block are registered. registering out- puts helps the synthesis tool to consider the implementation of the combinatorial logic and registers into the same logic block. registering outputs also makes the application of timing constraints easier since it eliminates possible problems with logic optimization across design boundaries. single clock is recommended for each synchronous block because it signi?antly reduces the timing consideration in the block. it leaves the adjustment of the clock relationships of the whole design at the top level of the hierarchy. figure 16-1 shows an example of synchronous blocks with registered outputs. figure 16-1. synchronous blocks with registered outputs keep related logic together in the same block keeping related logic and sharable resources in the same block allows the sharing of common combinatorial terms and arithmetic functions within the block. it also allows the synthesis tools to optimize the entire critical path in a single operation. since synthesis tools can only effectively handle optimization of certain amounts of logic, optimi- zation of critical paths pending across the boundaries may not be optimal. figure 16-2 shows an example of merg- ing sharable resource in the same block. figure 16-2. merge sharable resource in the same block separate logic with different optimization goals separating critical paths from non-critical paths may achieve ef?ient synthesis results. at the beginning of the project, one should consider the design in terms of performance requirements and resource requirements. if there ab c ab ab c ab mux mux + + +
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-3 are two portions of a block, one that needs to be optimized for area and a second that needs to be optimized for speed, they should be separated into two blocks. by doing this, different optimization strategies for each module can be applied without being limited by one another. keep logic with the same relaxation constraints in the same block when a portion of the design does not require high performance, this portion can be applied with relaxed timing constraints such as ?ulticycle to achieve high utilization of device area. relaxation constraints help to reduce overall run time. they can also help to ef?iently save resources, which can be used on critical paths. figure 16-3 shows an example of grouping logic with the same relaxation constraint in one block. figure 16-3. logic with the same relaxation constraint keep instantiated code in separate blocks it is recommended that the ram block in the hierarchy be left in a separate block (figure 16-4). this allows for easy swapping between the ram behavioral code for simulation, and the code for technology instantiation. in addition, this coding style facilitates the integration of the isplever ipexpress tool into the synthesis process. figure 16-4. separate ram block keep the number fpga gates at 30 to 80 pfu per block this range varies based on the computer con?uration, time required to complete each optimization run, and the targeted fpga routing resources. although a smaller block methodology allows more control, it may not produce the most ef?ient design since it does not provide the synthesis tool enough logic to apply ?esource sharing algorithms. on the other hand, having a large number of gates per block gives the synthesis tool too much to work on and causes changes that affect more logic than necessary in an incremental or multi-block design ?w. state encoding methodologies for state machines there are several ways to encode a state machine, including binary encoding, gray-code encoding and one-hot encoding. state machines with binary or gray-code encoded states have minimal numbers of ?p-?ps and wide combinatorial functions, which are typically favored for cpld architectures. however, most fpgas have many ?p- ?ps and relatively narrow combinatorial function generators. binary or gray-code encoding schemes can result in inef?ient implementation in terms of speed and density for fpgas. on the other hand, one-hot encoded state machine represents each state with one ?p-?p. as a result, it decreases the width of combinatorial logic, which matches well with fpga architectures. for large and complex state machines, one-hot encoding usually is the preferable method for fpga architectures. for small state machines, binary encoding or gray-code encoding may be more ef?ient. there are many ways to ensure the state machine encoding scheme for a design. one can hard code the states in the source code by specifying a numerical value for each state. this approach ensures the correct encoding of the state machine but is more restrictive in the coding style. the enumerated coding style leaves the ?xibility of state machine encoding to the synthesis tools. most synthesis tools allow users to de?e encoding styles either through a ff1 b ff2 ff1 a ff2 state machine counter controller ram register file to p
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-4 attributes in the source code or through the tools graphical user interface (gui). each synthesis tool has its own synthesis attributes and syntax for choosing the encoding styles. refer to the synthesis tools documentation for details about attributes syntax and values. the following syntax de?es an enumeration type in vhdl: type type_name is (state1_name,state2_name,......,staten_name) here is a vhdl example of enumeration states: type state_type is (s0,s1,s2,s3,s4); signal current_state, next_state : state_type; the following are examples of synplify and leonardospectrum vhdl synthesis attributes. synplify : attribute syn_encoding : string; attribute syn_encoding of : type is "value "; -- the syn_encoding attribute has 4 values : sequential, onehot, gray and safe. leonardospectr um : -- declare type_encoding_style attribute -- not needed if the exemplar_1164 package is used type encoding_style is (binary, onehot, gray, random, auto); attribute type_encoding_style : encoding_style; ... attribute type_encoding_style of : type is onehot; in verilog, one must provide explicit state values for states. this can be done by using the bit pattern (e.g., 3'b001), or by de?ing a parameter and using it as the case item. the latter method is preferable. the following is an exam- ple using parameter for state values. parameter state1 = 2'h1, state2 = 2'h2; ... current_state = state2; // setting current state to 2'h2 the attributes in the source code override the default encoding style assigned during synthesis. since verilog does not have prede?ed attributes for synthesis, attributes are usually attached to the appropriate objects in the source code as comments. the attributes and their values are case sensitive and usually appear in lower case. the follow- ing examples use attributes in verilog source code to specify state machine encoding style. synplify : reg[2:0] state; /* synthesis syn_encoding = "value" */; // the syn_encoding attribute has 4 values : sequential, onehot, gray and safe. in leonardospectrum, it is recommended to set the state machine variable to an enumeration type with enum pragma. once this is set in the source code, encoding schemes can be selected in the leonardospectrum gui. leonardospectr um : parameter /* exemplar enum */ s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4; reg [2:0] /* exemplar enum */ present_state, next_state ; in general, synthesis tools will select the optimal encoding style that takes into account the target device architec- ture and size of the decode logic. one can always apply synthesis attributes to override the default encoding style if necessary.
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-5 coding styles for fsm a ?ite state machine (fsm) is a hardware component that advances from the current state to the next state at the clock edge. as mentioned in the encoding methodologies for state machines section, the preferable scheme for fpga architectures is one-hot encoding. this section discusses some common issues encountered when con- structing state machines, such as initialization and state coverage, and special case statements in verilog. general state machine description generally, there are two approaches to describe a state machine. one is to use one process/block to handle both state transitions and state outputs. the other is to separate the state transition and the state outputs into two differ- ent process/blocks. the latter approach is more straightforward because it separates the synchronous state regis- ters from the decoding logic used in the computation of the next state and the outputs. this will make the code easier to read and modify, and makes the documentation more ef?ient. if the outputs of the state machine are combinatorial signals, the second approach is almost always necessary because it will prevent the accidental reg- istering of the state machine outputs. the following examples describe a simple state machine in vhdl and verilog. in the vhdl example, a sequential process is separated from the combinatorial process. in verilog code, two always blocks are used to describe the state machine in a similar way. vhdl example for state machine . . . architecture lattice_fpga of dram_refresh is type state_typ is (s0, s1, s2, s3, s4); signal present_state, next_state : state_typ; begin -- process to update the present state registers: process (clk, reset) begin if (reset='1') then present_state <= s0; elsif clk'event and clk='1' then present_state <= next_state; end if; end process registers; -- process to calculate the next state & output transitions: process (present_state, refresh, cs) begin ras <= '0'; cas <= '0'; ready <= '0'; case present_state is when s0 => ras <= '1'; cas <= '1'; ready <= '1'; if (refresh = '1') then next_state <= s3; elsif (cs = '1') then next_state <= s1; else next_state <= s0; end if; when s1 => ras <= '0'; cas <= '1'; ready <= '0'; next_state <= s2; when s2 => ras <= '0'; cas <= '0'; ready <= '0'; if (cs = '0') then next_state <= s0; else next_state <= s2; end if; when s3 => ras <= '1'; cas <= '0'; ready <= '0'; next_state <= s4; when s4 => ras <= '0'; cas <= '0'; ready <= '0'; next_state <= s0; when others => ras <= '0'; cas <= '0'; ready <= '0'; next_state <= s0; end case; end process transitions; . . . verilog example for state machine . . . parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4; reg [2:0] present_state, next_state; reg ras, cas, ready; // always block to update the present state always @ (posedge clk or posedge reset) begin if (reset) present_state = s0; else present_state = next_state; end // always block to calculate the next state & outputs always @ (present_state or refresh or cs) begin next_state = s0; ras = 1'bx; cas = 1'bx; ready = 1'bx; case (present_state) s0 : if (refresh) begin next_state = s3; ras = 1'b1; cas = 1'b0; ready = 1'b0; end else if (cs) begin next_state = s1; ras = 1'b0; cas = 1'b1; ready = 1'b0; end else begin next_state = s0; ras = 1'b1; cas = 1'b1; ready = 1'b1; end s1 : begin next_state = s2; ras = 1'b0; cas = 1'b0; ready = 1'b0; end s2 : if (~cs) begin next_state = s0; ras = 1'b1; cas = 1'b1; ready = 1'b1; end else begin next_state = s2; ras = 1'b0; cas = 1'b0; ready = 1'b0; end s3 : begin next_state = s4; ras = 1'b1; cas = 1'b0; ready = 1'b0; end s4 : begin next_state = s0; ras = 1'b0; cas = 1'b0; ready = 1'b0; end endcase end . . .
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-6 initialization and default state a state machine must be initialized to a valid state after power-up. this can be done at the device level during power up or by including a reset operation to bring it to a known state. for all lattice semiconductor fpga devices, the global set/reset (gsr) is pulsed at power-up, regardless of the function de?ed in the design source code. in the above example, an asynchronous reset can be used to bring the state machine to a valid initialization state. in the same manner, a state machine should have a default state to ensure the state machine will not go into an invalid state if not all the possible combinations are clearly de?ed in the design source code. vhdl and verilog have different syntax for default state declaration. in vhdl, if a case statement is used to construct a state machine, ?hen others should be used as the last statement before the end of the statement, if an if-then- else statement is used, ?lse should be the last assignment for the state machine. in verilog, use ?efault as the last assignment for a case statement, and use ?lse for the if-then-else statement. full case and parallel case speci?ation in verilog verilog has additional attributes to de?e the default states without writing it speci?ally in the code. one can use ?ull_case to achieve the same performance as ?efault? the following examples show the equivalent representa- tions of the same code in synplify. leonardospectrum allows users to apply verilog-speci? options in the gui set- tings. ?arallel_case makes sure that all the statements in a case statement are mutually exclusive. it is used to inform the synthesis tools that only one case can be true at a time. the syntax for this attribute in synplify is as follows: // synthesis parallel_case using pipelines in the designs pipelining can improve design performance by restructuring a long data path with several levels of logic and break- ing it up over multiple clock cycles. this method allows a faster clock cycle by relaxing the clock-to-output and setup time requirements between the registers. it is usually an advantageous structure for creating faster data paths in register-rich fpga devices. knowledge of each fpga architecture helps in planning pipelines at the when others in vhdl ... architecture lattice_fpga of fsm1 is type state_typ is (deflt, idle, read, write); signal next_state : state_typ; begin process(clk, rst) begin if (rst='1') then next_state <= idle; dout <= '0'; elsif (clk'event and clk='1') then case next_state is when idle => next_state <= read; dout <= din(0); when read => next_state <= write; dout <= din(1); when write => next_state <= idle; dout <= din(2); when others => next_state <= deflt; dout <= '0'; end case; end if; end process; ... default clause in verilog ... // define state labels explicitly parameter deflt=2'bxx; parameter idle =2'b00; parameter read =2'b01; parameter write=2'b10; reg [1:0] next_state; reg dout; always @(posedge clk or posedge rst) if (rst) begin next_state <= idle; dout <= 1'b0; end else begin case(next_state) idle: begin dout <= din[0]; next_state <= read; end read: begin dout <= din[1]; next_state <= write; end write: begin dout <= din[2]; next_state <= idle; end default: begin dout <= 1'b0; next_state <= deflt; end ? case (current_state) // synthesis full_case 2?b00 : next_state <= 2?b01; 2?b01 : next_state <= 2?b11; 2?b11 : next_state <= 2?b00; ? ? case (current_state) 2?b00 : next_state <= 2?b01; 2?b01 : next_state <= 2?b11; 2?b11 : next_state <= 2?b00; default : next_state <= 2bx;
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-7 beginning of the design cycle. when the pipelining technique is applied, special care must be taken for the rest of the design to account for the additional data path latency. the following illustrates the same data path before (figure 16-5) and after pipelining (figure 16-6). figure 16-5. before pipelining figure 16-6. after pipelining before pipelining, the clock speed is determined by the clock-to-out time of the source register, the logic delay through four levels of combinatorial logic, the associated routing delays, and the setup time of the destination regis- ter. after pipelining is applied, the clock speed is signi?antly improved by reducing the delay of four logic levels to one logic level and the associated routing delays, even though the rest of the timing requirements remain the same. it is recommended to check the place and route timing report to ensure that the pipelined design gives the desired performance. comparing if statement and case statement case and if-then-else statements are common for sequential logic in hdl designs. the if-then-else state- ment generally generates priority-encoded logic, whereas the case statement implements balanced logic. an if- then-else statement can contain a set of different expressions while a case statement is evaluated against a common controlling expression. both statements will give the same functional implementation if the decode condi- tions are mutually exclusive, as shown in the following vhdl codes. ff1 ff1 comb. function comb. function slow clock comb. function ff1 ff2 comb. function ff3 comb. function ff4 comb. function fast clock -- case statement ? mutually exclusive conditions process (s, x, y, z) begin o1 <= ?0?; o2 <= ?0?; o3 <= ?0?; case (s) is when ?00? => o1 <= x; when ?01? => o2 <= y; when ?10? => o3 <= z; end case; end process; -- if-then-else ? mutually exclusive conditions process (s, x, y, z) begin o1 <= ?0?; o2 <= ?0?; o3 <= ?0?; if s = ?00? then o1 <= x; elsif s = ?01? then o2 <= y; elsif s = ?10? then o3 <= z; end if; end process;
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-8 however, the use of if-then-else construct could be a key pitfall to make the design more complex than necessary, because extra logic are needed to build a priority tree. consider the following examples: if the decode conditions are not mutually exclusive, if-then-else construct will cause the last output to be dependent on all the control signals. the equation for o3 output in example a is: o3 <= z and (s3) and (not (s1 and s2)); if the same code can be written as in example b, most of the synthesis tools will remove the priority tree and decode the output as: o3 <= z and s3; this reduces the logic requirement for the state machine decoder. if each output is indeed dependent of all of the inputs, it is better to use a case statement since case statements provide equal branches for each output. avoiding non-intentional latches synthesis tools infer latches from incomplete conditional expressions, such as an if-then-else statements with- out an else clause. to avoid non-intentional latches, one should specify all conditions explicitly or specify a default assignment. otherwise, latches will be inserted into the resulting rtl code, requiring additional resources in the device or introducing combinatorial feedback loops that create asynchronous timing problems. non-intentional latches can be avoided by using clocked registers or by employing any of the following coding techniques: assigning a default value at the beginning of a process assigning outputs for all input conditions using else, (when others) as the ?al clause another way to avoid non-intentional latches is to check the synthesis tool outputs. most of the synthesis tools give warnings whenever there are latches in the design. checking the warning list after synthesis will save a tremen- dous amount of effort in trying to determine why a design is so large later in the place and route stage. hdl design with lattice semiconductor fpga devices the following section discusses the hdl coding techniques utilizing speci? lattice semiconductor fpga system features. this kind of architecture-speci? coding style will further improve resource utilization and enhance the performance of designs. lattice semiconductor fpga synthesis library the lattice semiconductor fpga synthesis library includes a number of library elements to perform speci? logic functions. these library elements are optimized for lattice semiconductor fpgas and have high performance and utilization. the following are the classi?ations of the library elements in the lattice semiconductor fpga synthe- --a: if-then-elese statement: complex o3 equations process(s1, s2, s3, x, y, z) begin o1 <= ?0?; o2 <= ?0?; o3 <= ?0?; if s1 = ?1? then o1 <= x; elsif s2 = ?1? then o2 <= y; elsif s3 = ?1? then o3 <= z; end if; end process; --b: if-then-else statement: simplified o3 equation process (s1, s2, s3, x, y, z) begin o1 <= ?0?; o2 <= ?0?; o3 <= ?0?; if s1 = ?1? then o1 <= x; end if; if s2 = ?1? then o2 <= y; end if; if s3 <= ?1? then o3 <= z; end if; end process;
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-9 sis library. the de?itions of these library elements can be found in the reference manuals section of the isplever on-line help system. logic gates and luts comparators, adders, subtractors counters flip-?ps and latches memory, 4e-speci? memory (block ram function) multiplexors multipliers all i/o cells, including i/o ?p-?ps pic cells special cells, including pll, gsr, boundary scan, etc. fpsc elements ipepxress, a parameterized module complier optimized for lattice fpga devices, is available for more complex logic functions. ipexpress supports generation of library elements with a number of different options such as plls and creates parameterized logic functions such as pfu and ebr memory, multipliers, adders, subtractors, and counters. ipexpress accepts options that specify parameters for parameterized modules such as data path mod- ules and memory modules, and produces a circuit description with lattice semiconductor fpga library elements. output from ipexpress can be written in edif, vhdl, or verilog. in order to use synthesis tools to utilize the lattice fpga architectural features, it is strongly recommended to use ipexpress to generate modules for source code instantiation. the following are examples of lattice semiconductor fpga modules supported by ipexpress: pll memory implemented in pfu: ?synchronous single-port ram, synchronous dual-port ram, synchronous rom, synchronous fifo memory implemented with ebr: quad-port block ram, dual-port block ram, single-port block ram, rom, fifo other ebr based functions multiplier, cam pfu based functions multiplier, adder, subtractor, adder/subtractor, linear feedback shifter, counter mpi/system bus ipexpress is especially ef?ient when generating high pin count modules as it saves time in manually cascading small library elements from the synthesis library. detailed information about ipexpress and its user guide can be found in the isplever help system.
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-10 implementing multiplexers the ?xible con?urations of luts can realize any 4-, 5-, or 6-input logic function like 2-to-1, 3-to-1 or 4-to-1 multi- plexers. larger multiplexers can be ef?iently created by programming multiple 4-input luts. synthesis tools camn automatically infer lattice fpga optimized multiplexer library elements based on the behavioral description in the hdl source code. this provides the ?xibility to the mapper and place and route tools to con?ure the lut mode and connections in the most optimum fashion. clock dividers there are two ways to implement clock dividers in lattice semiconductor fpga devices. the ?st is to cascade the registers with asynchronous clocks. the register output feeds the clock pin of the next register (figure 16-7). since the clock number in each pfu is limited to two, any clock divider with more than two bits will require multiple pfu implementations. as a result, the asynchronous daisy chaining implementation of clock divider will be slower due to the inter-plc routing delays. this kind of delays is usually ambiguous and inconsistent because of the nature of fpga routing structures. figure 16-7. daisy chaining of flip-?ps 16:1 mux ? process(sel, din) begin if (sel="0000") then muxout <= din(0); elsif (sel="0001") then muxout <= din(1); elsif (sel="0010") then muxout <= din(2); elsif (sel="0011") then muxout <= din(3); elsif (sel="0100") then muxout <= din(4); elsif (sel="0101") then muxout <= din(5); elsif (sel="0110") then muxout <= din(6); elsif (sel="0111") then muxout <= din(7); elsif (sel="1000") then muxout <= din(8); elsif (sel="1001") then muxout <= din(9); elsif (sel="1010") then muxout <= din(10); elsif (sel="1011") then muxout <= din(11); elsif (sel="1100") then muxout <= din(12); elsif (sel="1101") then muxout <= din(13); elsif (sel="1110") then muxout <= din(14); elsif (sel="1111") then muxout <= din(15); else muxout <= '0'; end if; end process; ? lu lu pfu pfu d d
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-11 the following are the hdl representations of the design in figure 16-7. the preferable way is to fully employ the plc's natural ?ipple-mode? a single pfu can support up to 8-bit ripple functions with fast carry logic. figure 16-8 is an example of 4-bit counter in plc ?ipple mode? in lattice semicon- ductor fpga architectures, an internal generated clock can get on the clock spine for small skew clock distribution, further enhancing the performance of the clock divider. figure 16-8. use plc ?ipple mode here are the hdl representations of the design in figure 16-8. -- vhdl example of daisy chaining ff ... -- 1st ff to divide clock in half clk_div1: process(clk, rst) begin if (rst='1') then clk1 <= '0'; elsif (clk'event and clk='1') then clk1 <= not clk1; end if; end process clk_div1; -- 2nd ff to divide clock in half clk_div2: process(clk1, rst) begin if (rst='1') then clk2 <= '0'; elsif (clk1'event and clk1='1') then clk2 <= not clk2; end if; end process clk_div2; //verilog example of daisy chaining ff ... always @(posedge clk or posedge rst) begin if (rst) clk1 = 1'b0; else clk1 = !clk1; end always @(posedge clk1 or posedge rst) begin if (rst) clk2 = 1'b0; else clk2 = !clk2; end ... divby2 divby4 divby8 divby16 lut in ripple mode 4-bit counter -- vhdl : ?ripplemode? clock divider ... count4: process(clk, rst) begin if (rst='1') then cnt <= (others=>'0'); elsif (clk'event and clk='1') then cnt <= cnt + 1; end if; end process count4; divby4 <= cnt(1); divby16 <= cnt(3); //verilog : ?ripplemode? clock divider ... always @(posedge clk or posedge rst) begin if (rst) cnt = 4'b0; else cnt = cnt + 1'b1; end assign divby4 = cnt[1]; assign divby16 = cnt[3]; ...
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-12 register control signals the general-purpose latches/ffs in the pfu are used in a variety of con?urations depending on device family. for example, the lattice ec, ecp, sc and xp family of devices clock, clock enable and lsr control can be applied to the registers on a slice basis. each slice contains two lut4 lookup tables feeding two registers (programmed asto be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (prgorammable as syn- chronous/asynchronous), clock select, chip-select and wider ram/rom functions. the orca series 4 family of devices clock, clock enable and lsr control can be applied to the registers on a nibble-wide basis. when writing design codes in hdl, keep the architecture in mind to avoid wasting resources in the device. here are several points for consideration: if the register number is not a multiple of 2 or 4 (dependent on device family), try to code the registers in a way that all registers share the same clock, and in a way that all registers share the same control signals. lattice semiconductor fpga devices have multiple dedicated clock enable signals per pfu. try to code the asynchronous clocks as clock enables, so that pfu clock signals can be released to use global low- skew clocks. try to code the registers with local synchronous set/reset and global asynchronous set/reset for more detailed architecture information, refer to the lattice semiconductor fpga data sheets. clock enable figure 16-9 shows an example of gated clocking. gating clock is not encouraged in digital designs because it may cause timing issues such as unexpected clock skews. the structure of the pfu makes the gating clock even more undesirable since it will use up all the clock resources in one pfu and sometimes waste the ff/ latches resources in the pfu. by using the clock enable in the pfu, the same functionality can be achieved without worrying about timing issues as only one signal is controlling the clock. since only one clock is used in the pfu, all related logic can be implemented in one block to achieve better performance. figure 16-10 shows the design with clock enable signal being used. figure 16-9. asynchronous: gated clocking figure 16-10. synchronous: clock enabling the vhdl and verilog coding for clock enable are as shown in figure 16-10. dq din qout clk gate d s a b q din qout clk clken -- vhdl example for clock enable ... clock_enable: process(clk) begin if (clk'event or clk='1') then if (clken='1') then qout <= din; end if; end if; end process clock_enable; // verilog example for clock enable ... always @(posedge clk) qout <= clken ? din : qout; ...
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-13 the following are guidelines for coding the clock enable in lattice semiconductor fpgas: clock enable is only supported by ffs, not latches. nibble wide ffs and slices inside a plc share the same clock enable all ?p-?ps in the lattice semiconductor fpga library have a positive clock enable signal in the orca series 4 architecture, the clock enable signal has the higher priority over synchronous set/reset by default. however, it can be programmed to have the priority of synchronous lsr over the prior- ity of clock enable. this can be achieved by instantiating the library element in the source code. for exam- ple, the library element fd1p3ix is a ?p-?p that allows synchronous clear to override clock enable. users can also specify the priority of generic coding by setting the priority of the control signals differently. the following examples demonstrate coding methodologies to help the synthesis tools to set the higher pri- ority of clock enable or synchronous lsr. set / reset there are two types of set/reset functions in lattice semiconductor fpgas: global (gsr) and local (lsr). the gsr signal is asynchronous and is used to initialize all registers during con?uration. it can be activated either by an external dedicated pin or from internal logic after con?uration. the local set/reset signal may be synchronous or asynchronous. gsr is pulsed at power up to either set or reset the registers depending on the con?uration of the device. since the gsr signal has dedicated routing resources that connect to the set and reset pin of the ?p- ?ps, it saves general-purpose routing and buffering resources and improves overall performance. if asynchronous reset is used in the design, it is recommended to use the gsr for this function, if possible. the reset signal can be forced to be gsr by the instantiation library element. synthesis tools will automatically infer gsr if all registers in -- vhdl example of sync. lsr over ce ... count8: process(clk, grst) begin if (grst = '1') then cnt <= (others => '0'); elsif (clk'event and clk='1') then -- lsr over ce: sync. set/reset has higher priority if (lrst = '1') then cnt <= (others => '0'); elsif (cken = '1') then cnt <= cnt + 1; end if; // verilog example of sync. lsr over ce ... always @(posedge clk or posedge grst) begin if (grst) cnt = 4'b0; else if (lrst) cnt = 4'b0; else if (cken) cnt = cnt + 1'b1; end ... -- vhdl example of ce over sync. lsr ... count8: process(clk, grst) begin if (grst = '1') then cnt <= (others => '0'); elsif (clk'event and clk='1') then -- ce over lsr: clock enable has higher priority if (cken = '1') then cnt <= cnt + 1; elsif (lrst = '1') then cnt <= (others =>'0'); end if; end if; e n d p r ocess cou nt 8; // verilog example of ce over sync. lsr ... always @(posedge clk or posedge grst) begin if (grst) cnt = 4'b0; else if (cken) cnt = cnt + 1'b1; else if (lrst) cnt = 4'b0; end...
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-14 the design are asynchronously set or reset by the same wire. the following examples show the correct syntax for instantiating gsr in the vhdl and verilog codes. use pic features using i/o registers/latches in pic moving registers or latches into input/output cells (pic) may reduce the number of plcs used and decrease rout- ing congestion. in addition, it reduces setup time requirements for incoming data and clock-to-output delay for out- put data, as shown in figure 16-11. most synthesis tools will infer input registers or output registers in pic if possible. users can set synthesis attributes in the speci? tools to turn off the auto-infer capability. users can also instantiate library elements to control the implementation of pic resource usage. figure 16-11. moving ff into pic input register figure 16-12. moving ff into pic output register // verilog example of gsr instantiation module gsr_test(clk, rst, cntout); input clk, rst; output[1:0] cntout; reg[1:0] cnt; gsr u1 (.gsr(rst)); always @(posedge clk or negedge rst) begin if (!rst) cnt = 2'b0; else cnt = cnt + 1; end assign cntout = cnt; endmodule -- vhdl example of gsr instantiation library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity gsr_test is port (rst, clk: in std_logic; cntout : out std_logic_vector(1 downto 0)); end gsr_test; architecture behave of gsr_test is signal cnt : std_logic_vector(1 downto 0); begin u1: gsr port map (gsr=>rst); process(clk, rst) begin if rst = '1' then cnt <= "00"; elsif rising_edge (clk) then cnt <= cnt + 1; end if; end process; cntout <= cnt; end behave; d q in_sig pic before using input register plc d q in_sig pic after using input register d q out_sig pic pic before using output register plc d q out_sig after using output register
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-15 inferring bi-directional i/o users can either structurally instantiate the bi-directional i/o library elements, or behaviorally describe the i/o paths to infer bi-directional buffers. the following vhdl and verilog examples show how to infer bi-directional i/o buffers. specifying i/o types and locations users can either assign i/o types and unique i/o locations in the preference editor or specify them as attributes in the vhdl or verilog source code. the following examples show how to add attributes in the synplify and leonar- dospectrum synthesis tool sets. for a complete list of supported attributes, refer to the hdl attributes section of the isplever on-line help system. -- vhdl example of specifying i/o type and location attributes for synplify & leonardo entity cnt is port(clk: in std_logic; res: out std_logic); attribute levelmode: string: attribute levelmode of clk : signal is ?stl2? attribute loc of clk : signal is ?2? attribute levelmode of res : signal is ?stl2? attribute loc of res : signal is ?3? end entity cnt; -- verilog example of specifying i/o type and location attributes for synplify & leonardo module cnt(clk,res); input clk /* synthesis levelmode=?stl2 loc=?2?/; output res /* synthesis levelmode=?stl2 loc=?3 */; ... // exemplar begin // exemplar attribute clk levelmode sstl2 // exemplar attribute clk loc v2 // exemplar attribute res levelmode sstl2 // exemplar attribute res loc v3 // exemplar end endmodule // inferring bi-directional i/o in verilog module bidir_infer (a, b, dir); inout a, b; input dir; assign b = (dir) ? a : 1'bz; assign a = (~dir) ? b : 1'bz; endmodule -- inferring bi-directional i/o in vhdl library ieee; use ieee.std_logic_1164.all; entity bidir_infer is port(a, b : inout std_logic; dir : in std_logic); end bidir_infer; architecture lattice_fpga of bidir_infer is begin b <= a when (dir='1') else 'z'; a <= b when (dir='0') else 'z'; end lattice_fpga
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-16 implementation of memories although an rtl description of ram is portable and the coding is straightforward, it is not recommended because the structure of ram blocks in every architecture is unique. synthesis tools are not optimized to handle ram imple- mentation and thus generate inef?ient netlists for device ?ting. for lattice semiconductor fpga devices, ram blocks should be generated through ipexpress as shown in the following screen shot. when implementing large memories in the design, it is recommended to construct the memory from the enhanced block ram (ebr) components found in every lattice semiconductor fpga device. when implementing small memories in the design, it is recommended to construct the memory from the resources in the pfu. the memory utilizing resources in the pfu can also be generated by ipexpress. lattice semiconductor fpgas support many different memory types including synchronous dual-port ram, syn- chronous single-port ram, synchronous fifo and synchronous rom. for more information on supported mem- ory types per fpga architecture, please consult the lattice semiconductor fpga data sheets. preventing logic replication and limited fanout lattice semiconductor fpga device architectures are designed to handle high signal fanouts. when users make use of clock resources, there will be no hindrance on fanout problems. however, synthesis tools tend to replicate logic to reduce fanout during logic synthesis. for example, if the code implies clock enable and is synthesized with speed constraints, the synthesis tool may replicate the clock enable logic. this kind of logic replication occupies more resources in the devices and makes performance checking more dif?ult. it is recommended to control the logic replication in synthesis process by using attributes for high fanout limit.
hdl synthesis coding guidelines lattice semiconductor for lattice semiconductor fpgas 16-17 in the synplicity project gui, under the implementation options => devices tab, users can set the fanout guide value to 1000 instead of using the default value of 100. this will guide the tool to allow high fanout signals without replicating the logic. in the leonardospectrum tool project gui, under technology => advanced settings, users can set the max fanout to be any number instead of the default value ?? use isplever project navigator results for device utilization and performance many synthesis tools give usage reports at the end of a successful synthesis. these reports show the name and the number of library elements used in the design. the data in these reports do not represent the actual implemen- tation of the design in the ?al place and route tool because the edif netlist will be further optimized during map- ping and place and route to achieve the best results. it is strongly recommended to use the map report and the par report in the isplever project navigator tool to understand the actual resource utilization in the device. although the synthesis report also provides a performance summary, the timing information is based on estimated logic delays only. the place & route trace report in the isplever project navigator gives accurate perfor- mance analysis of the design by including actual logic and routing delays in the paths. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
www.latticesemi.com 17-1 tn1010_02.0 july 2004 technical note tn1010 introduction lattice semiconductors isplever software, together with lattice semiconductors catalog of programmable devices, provides options to help meet design timing and logic utilization requirements. additionally, for those instances where objectives push the capabilities of the device architecture, isplever provides the tools for meet- ing the most challenging requirements. for the most aggressive design requirements, the designer should become familiar with a variety of timing con- straints (called preferences) and place and route (par) techniques for providing the optimal par results as dis- cussed in technical note number tn1018, lattice semiconductor successful place and route. if performance goals cannot be met with fpga timing preferences and additional levels of the place & route design process, improved performance can be achieved by directing the physical layout of the circuit in the fpga. this step, often referred to as ?orplanning, is done by specifying fpga location preferences. this application note explains what ?orplanning is, when it should be used, and how it is done with respect to lat- tice semiconductor fpga designs. this document is divided into four major sections: floorplanning de?ition, logical and physical when to ?orplan, general versus speci? reasons how to ?orplan: grouping constraints, examples, and floorplanner gui presentation special considerations, large and special groupings supported architectures floorplanning can be done on all lattice semiconductor fpga architectures. related documentation designers are encouraged to reference the isplever on-line documentation. floorplanning de?ition floorplanning a digital logic design for implementation in a programmable device involves the physical or logical partitioning of the design elements which results in a change in the physical placement or implementation of the design elements. in other words, ?orplanning is the grouping of design elements in a certain way to improve the performance of a design. with lattice semiconductor fpgas, ?orplanning is an optional methodology to help designers improve the perfor- mance and density of a fully, automatically placed and routed design. floorplanning is particularly useful in struc- tured designs and data path logic. design ?orplanning is very powerful and provides a combination of automation and user control for design reuse and modular, hierarchical, and incremental design ?ws. complex fpga design management lattice semiconductor fpgas can implement large system designs that contain millions of gates, hundreds of thousands of embedded memory bits, and intellectual property (ip) components. design teams often work on large designs. the design complexity requires eda tools to manage and optimize the design. large design management is dif?ult, but performance optimization is even more dif?ult. optimization requires many design iterations when adding or modifying components. complex, large system designs require the following: the use of modular, hierarchical, or incremental design methods software that makes management and optimization easier lattice semiconductor design floorplanning
lattice semiconductor lattice semiconductor design floorplanning 17-2 use of ip blocks reuse of previously optimized design elements by controlling the placement of speci?d logic elements, design ?orplanning methodologies help designers meet the requirements of large system design. floorplanning design flow in both traditional and ?orplanning fpga design ?ws, the designer divides the system into modules. the mod- ules can be individual circuits, parts of circuits, or parts of the design hierarchy. after module design and optimiza- tion, the designer integrates the modules into the system. finally, the designer tests and optimizes the system. in the traditional ?w, the system may not meet performance requirements even if each module meets the require- ments before integration. even when timing requirements have been satis?d, changes to one module can affect the performance of others. re-optimizing modules to meet system performance results in many design iterations. floorplanning methodologies assist in the design, testing, and optimization of each individual module while retain- ing the optimized characteristics of the individual modules. module integration into the system requires only system optimization between modules. the ?orplanning methodologies provide additional ?xibility by allowing the isplever software to automatically place de?ed modules, or allowing the user to control the placement of spe- ci? modules, which provide performance preservation and optimization. when to floorplan floorplanning methodologies are intended to assist users who require some degree of handcrafting for their designs. the designer must understand both the details of the device architectures and the ways ?orplanning can be used to re?e a design. successful ?orplanning is very much an iterative process and it can take time to develop a ?orplan that outperforms an automatic, software processed design. because of the nature of ?orplan- ning and its interaction with the automatic map and par software tools, several prerequisites are necessary in order to ?orplan a design successfully. detailed knowledge of the speci?s of the target architecture and device detailed knowledge of the speci?s of the design being implemented a design that lends itself to ?orplanning a willingness to iterate a ?orplan to achieve the desired results realistic performance and density goals for lattice semiconductor fpgas, the general rule-of-thumb is that ?orplanning should be considered when the performance needed cannot be met and routing delays account for over 60 % of the critical path delays. that is, interacting components are too far apart in the fpga array to achieve short routing delays. this has shown to be a problem especially with large designs in high density fpgas because of the possibilities of long distance routes. as programmable logic design densities continue to escalate beyond 100,000 gates, traditional design ?w design entry to synthesis to place and route ?will sometimes not yield predictable, timely, and optimized results. note that the guidelines discussed above only apply to designs that have been routed by the software for several routing iterations. the default number of routing iterations via the isplever project navigator is variable depend- ing on the lattice semiconductor fpga device family chosen. a note on delays: path delays in programmable devices are made up of two parts: logical delays and routing delays. logical delays in this context are delays through components, such as a a programmable function unit (pfu), a programmable input/output (pio), a slice, or an embedded function (i.e. a block ram, pll, or embedded fpsc asic). the routing delay is the delay of the interconnect between components. figures 1 and 2 show delay examples from timing wizard report ?es (.twr).
lattice semiconductor lattice semiconductor design floorplanning 17-3 figure 17-1. floorplanning may be able to help bring these registers closer figure 17-2. floorplanning is not needed here because the routing is ef?ient floorplan to improve design performance properly applied, design ?orplanning not only preserves, but improves design performance. floorplanning meth- odologies can be used to place modules, entities, or any group of logic to regions in a devices ?orplan. because ?orplanning assignments can be hierarchical, designers can have more control over the placement and perfor- mance of modules and groups of modules. in addition to hierarchical blocks, like grouping an entire vhdl entity or verilog module, designers can ?orplan individual nodes (e.g., instantiate a library element for a function in the critical path and then group the library ele- ment). this technique is useful if the critical path spans multiple design blocks. note: although ?orplanning can increase performance, it may also degrade performance if it is not applied cor- rectly within software limitations. floorplan to preserve module performance floorplanning with design constraints maintains design performance by grouping the placement of nodes in a device, i.e., the relative placement of logic within a grouped region remains constant. the isplever software then places the grouped region into the top-level design with these constraints. when placing logic in a region, the isplever software does not preserve the routing information. this approach provides more ?xibility when the software imports the region into the top-level design and helps ?ting. floorplan for design reuse floorplanning facilitates design reuse by its ability to reproduce the performance of a module designed in a differ- ent project. for frequently used modules, designers can create a library of veri?d designs that can be incorpo- rated into other larger designs. the library only has to contain the vhdl or verilog source code along with grouping attributes and some comments detailing useful information to the user, such as performance and size. with a parameterized module, in-code assignments can specify the modules size and grouping assignments. targeting the same device used in the original design likely achieves the best results, although other devices in the same family will likely work well. when using a different device in the same family, the exact placement of the region may not be possible. similar performance, however, may be possible by moving or ?ating regions. a ?at- ing region groups the logic together and guides the isplever software toward achieving a placement that meets the performance requirements of the module. a similar approach can also be taken if exact placement of a module is not applicable because of multiple instantiations of a module in a top-level design. logical details: cell type pin type cell name (clock net +/-) source: ff q ibuf/reg_init_start (from clk_ib+) destination: ff data in ibuf/sd/reg_new_state (to clk_ib +) delay: 8.062ns (18.2% logic, 81.8% route), 2 logic levels. logical details: cell type pin type cell name (clock net +/-) source: ff q mem_if_tx_address_8 (from clk_c +) destination: ff data in mem_if_tx_address_17 (to clk_c +) delay: 7.358ns (61.2% logic, 38.8% route), 4 logic levels.
lattice semiconductor lattice semiconductor design floorplanning 17-4 how to floorplan a design design performance enhancement strategies floorplanning methodologies improve the performance of designs that do not necessarily consist of individually optimized modules. the ability of specifying regions to group nodes together and provide relative placement enhances the usability of the isplever place-and-route software tools. the design strategies for performance enhancement depend on the structure of a particular circuit. strategies include: de?ing regions based on design hierarchy if the hierarchy closely resembles the structure of the circuit. these designs typically consist of tightly integrated modules, where the logic for each module is self-con- tained and modules communicate through well-de?ed interfaces. de?ing regions based on the critical path, if the critical path is long and spans multiple modules. keeping the nodes in the critical path or the modules containing the critical path together may lead to improved per- formance. de?ing regions based on connections by grouping nodes with high fan-outs and high fan-ins together to reduce delays in connections and wiring congestion in the device. note that designers may need to change existing design hierarchy and structure to make the design more amiable to ?orplanning. this is especially applicable if modular hierarchy and structure was not considered at the begin- ning of design conception. with the ?orplaning methodologies, the user can choose to optimize modules either individually or after they have been integrated with the top-level design. the user can exercise varying amounts of control over the placement by using different types of regions. by using bounding boxes and location anchors selectively, the isplever software can easily determine the best size and location for a region. another approach is to optimize the top-level design without ?st optimizing the individual modules. this approach allows the isplever software to place nodes within regions and move regions across the device. the user assigns modules to regions and then compiles the entire design. with this approach the user can place elements from different modules in a region. design floorplanning methodologies there are several methods available to aid in the ?orplanning of a logical design in a lattice semiconductor fpga. this section illustrates these methods with examples of how to use the isplever software tools to achieve performance goals. the three main ?orplanning tools available include: the pgroup physical constraint can be used as an attribute in vhdl and verilog hdl source code or as a physical preference in the .prf design constraint ?e. this can be used directly by the isplever placer software to bound and locate sections of a design for grouping in the fpga array. the ugroup logical constraint can be used as an attribute in vhdl and verilog hdl source code to gather logical sections of a design for grouping in the fpga array. the floorplanner graphical user interface (gui) can be used to interactively specify placement parame- ters in either the logical or physical domain for some of a designs modules (e.g. logic gates, registers, arith- metic functions) from one graphical user interface. when to use pgroup vs. ugroup ugrouping differs from pgrouping as follows: a pgroup logical identi?r, in edif, is prepended with text that describes the identi?rs hierarchy. a ugroup logical identi?r, in edif, is not changed by prepending the hierarchy on the block instance identi?r. in other words, pgrouping enforces strict hierarchical control while ugrouping allows for a grouping of blocks in different hierarchies or a grouping of blocks with no hierarchy at all.
lattice semiconductor lattice semiconductor design floorplanning 17-5 also note that the pgroup attribute can be placed on multiple instantiations of modules (e.g. vhdl generate statements) and each instantiation will have its own pgroup. using a ugroup will not work in this case. in figures 3 and 4, the arrows represent control and data paths where there is interaction between different levels of hierarchy. the thick lined arrow represents the critical path where the design is failing to make performance. figure 17-3. pgroup same hierarchy example, pgroup controller figure 17-3 illustrates a design hierarchy where the failing paths are the connections between counter and state_machine design blocks. the easiest implementation for this example is to pgroup the controller, which is the module in which the counter and state_machine are instantiated within. for example, if the following synplify attribute is in the verilog hdl ?e: module controller ()/* synthesis pgroup=?control_group? */; then the counter and state_machine will be grouped in the fpga inside a boundary box. now assume that the counter is mapped into pfu_0 and pfu_1 and the state_machine is mapped into pfu_2. the resulting preference generated by map in the .prf ?e will be: pgroup ?top/controller/control_group? comp ?pfu_0? comp ?pfu_1? comp ?pfu_2?; notice the top/ hierarchy is prepended to the controller pgroup identi?r. figure 17-4. ugroup different hierarchy example, ugroup register_file and state machine figure 17-4 shows an example design hierarchy where the failing paths are the connections between register_file and state_machine modules. the simplest thing to do here is to ugroup the register_file and state_machine together. for example, if the following synplify attributes are in the verilog hdl ?e: top level of hierarchy top controller counter critical path state_machine register_file second level of hierarchy third level of hierarchy top level of hierarchy top controller counter critical path state_machine register_file second level of hierarchy third level of hierarchy
lattice semiconductor lattice semiconductor design floorplanning 17-6 module register_file () /*synthesis ugroup=?critical_group? */; and module state_machine () /*synthesis ugroup=?critical_group? */; then the register_file and state_machine will be grouped in the fpga inside a default boundary box. now assume that the register_file is mapped into pfu_4 and pfu_5 and the state_machine is mapped into pfu_3. the resulting preference generated by map in the .prf ?e will be: pgroup ?critical_group? comp ?pfu_3? comp ?pfu_4? comp ?pfu_5?; notice the top/ hierarchy is not appended to the pgroup identi?r critical_group. also notice that ugroup attributes result in pgroup preferences. there is no ugroup preference. if pgroup attributes instead of ugroup attributes had been used for figure 17-4: module register_file () /*synthesis pgroup=?critical_group? */; and module state_machine () /*synthesis pgroup=?critical_group? */; then the resulting preference generated by map in the .prf ?e would be: pgroup ?top/controller/state_machine/critical_group? comp ?pfu_3? pgroup ?top/register_file/critical_group? comp ?pfu_4? comp ?pfu_5?; so, with pgroup attributes, the state_machine module would be grouped together in one bounding box and register_file module would be grouped together separately in another bounding box and the critical path shown in figure 17-4 will not be optimized. these examples do not utilize all the possible tools available for ?orplanning. please refer to isplever on-line help pgroup section for many small syntax examples. floorplanner gui usage generally, the pgroups and ugroups are preferable to the floorplanner gui since they are easier to imple- ment. for example, it is easier to type in a pgroup attribute in the hdl code then to load the gui with large netlists and ?d the desired block and perform add the pgroup via mouse clicks. more importantly, the gui does not allow the retention of ?orplanning the way pgrouping and ugrouping does. since the gui does not back annotate the grouping attributes into the hdl, the gui operations have to be redone every time there is a new design iteration. the floorplanner gui can be useful for viewing elements in a graphical environment to see a designs logical hierarchy. viewing existing pgroups and ugroups. resizing regions and boundary boxes (bboxes). graphically placing regions, pgroups, and ugroups and then running map, place, route, and trace to see the effects. this is usually an iterative process before ?ding an optimal solution.
lattice semiconductor lattice semiconductor design floorplanning 17-7 if the floorplanner gui is used, it is strongly recommended that after ?ding the optimal grouping with the gui, grouping attributes (pgroup and/or ugroups) should be inserted into the hdl source code to pre- serve module performance over design revisions. special floorplanning considerations embedded block ram placement block ram placement can be done with simple locate preferences. it is not always necessary to locate block rams. do not use the pgroups, ugroups, or the floorplanner gui to group block rams. i/o grouping there is a complete set of physical constraints on pgrouping i/o components. please refer to isplever on-line help, de?ing pio component groups, for keyword explanations and syntax examples. large module grouping it is strongly recommended that larger pgroups/ugroups (with many logical elements) be anchored and bounded by locate and bbox keywords. from the state_machine example, we see that without anchoring the groups, the performance worsened compared to no ?orplanning at all. the bbox should be strategically shaped and sized according to the module to be placed inside the bbox. if the bbox shape and size is not speci?d, the default bbox size will be a square that is as small as possible. this is not the optimal bbox for typical modules. the designer should shape the design with the datapath in mind and size the bbox to be larger then needed so that the isplever placer program can have more ?xibility in placing logic elements inside the bbox. carry chains and bus grouping carry chains (used by ripple arithmetic functions like adders, counters, and multipliers) and logic modules con- nected by busses can easily be ?orplanned inappropriately by a designer that is not aware of the internal routing resources available to optimize these carry chain and bus routes. as we saw from the multiplier example, certain groupings can reduce the performance of a design compared to no ?orplanning at all. great care should be used when ?orplanning designs that use carry chains or busses so that these routes fall in optimal locations for optimal performance. broken carry chain example a 9-bit adder that is pgrouped with no relative placement on the adder. logic elements such as pfus may give worse performance because the adder carry-chain is broken. slics in groups for lattice semiconductor fpga device families that contain supplemental logic and interconnect cells (slics), the slics are automatically removed from pgroups and ugroups by the isplever software if they are not rel- atively placed. this is because slics are used by the tools for interconnects that are not foreseeable by designers. if slic placement has to be controlled for a design, the designer will need to instantiate and locate the slics in their preference or hdl ?es. it is recommended to allow the isplever software to automatically place slics. summary this application note de?ed ?orplanning, discussed when it should be used, and detailed how ?orplanning is done with respect to lattice semiconductor fpga designs. examples were used to illustrate and compare the dif- ferent tools available to the designer for ?orplanning. important items discussed: floorplanning can improve timing for targeted critical paths. improper ?orplanning can make timing worse.
lattice semiconductor lattice semiconductor design floorplanning 17-8 correct ?orplanning can increase logic element count slightly. completed ?orplanning should be annotated into the hdl. floorplanning enhances the reusability of designs by keeping placement directives in the hdl. use pgroups for physical grouping in the same hierarchy. use ugroups for logical grouping across hierarchies. with lattice semiconductor fpgas, ?orplanning is an optional methodology to help designers improve perfor- mance and density of a fully, automatically placed and routed design. floorplanning is particularly useful on struc- tured designs and data path logic. design ?orplanning is very powerful and provides a combination of automation and user control for design reuse and modular, hierarchical, and incremental design ?ws. it advances the design of large systems on fpgas. it pro- vides the designer with capabilities in the management and optimization of large systems. its multifaceted capabil- ities result in shortened design cycles and faster time to market. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
www.latticesemi.com 18-1 tn1018_02.0 july 2004 technical note tn1018 introduction lattice semiconductors isplever software, together with lattice semiconductors catalog of programmable devices, provides options to help meet design timing and logic utilization requirements. additionally, for those instances where objectives push the capabilities of the device architecture, isplever provides the tools for meet- ing the most challenging requirements. for the most aggressive design requirements, the designer should become familiar with a variety of timing con- straints (called preferences) and place and route (par) techniques for providing the optimal par results. this document describes these tips and techniques. advanced techniques in ?orplanning will not be discussed in this document. instead they are covered in technical note number tn1010, lattice semiconductor design floorplan- ning . isplever place and route software (par) in the isplever design ?w, after a design has undergone the necessary translation to bring it into the mapped physical design (.ncd ?e) format, it is ready for placement and routing. this phase is handled by the timing-driven par software program. designers can invoke par from the isplever project navigator or from the command line. par performs the following: takes a mapped physical design (.ncd ?e) and a preference ?e (.prf) as input ?es. places and routes the design, attempting to meet the timing preferences in the input .prf ?e. creates a ?e which can then be processed by the isplever design implementation tools. placement the par process places the mapped physical design (.ncd ?e) in two stages: a constructive placement and an optimizing placement. par writes the physical design after each of these stages is complete. during constructive placement, par places components into sites based on factors such as: constraints speci?d in the input ?e (for example, certain components must be in certain locations). the length of connections. the available routing resources. cost tables which assign random weighted values to each of the relevant factors. there are 100 possible cost tables. constructive placement continues until all components are placed. optimizing placement is a ?e-tuning of the results of the constructive placement. routing routing is also done in two stages: iterative routing and delay reduction routing (also called cleanup). par writes the physical design (.ncd ?e) only after iterations where the routing score has improved. during iterative routing, the router performs an iterative procedure to converge on a solution that routes the design to completion or minimizes the number of unrouted nets. during cleanup routing (also called delay reduction), the router takes the results of iterative routing and reroutes some connections to minimize the signal delays within the device. there are two types of cleanup routing that can be performed: lattice semiconductor fpga successful place and route
lattice semiconductor fpga lattice semiconductor successful place and route 18-2 a faster cost-based cleanup routing, which makes routing decisions by assigning weighted values to the factors (for example, the type of routing resources used) affecting delay times between sources and loads. a more cpu-intensive, delay-based cleanup routing, which makes routing decisions based on computed delay times between sources and loads on the routed nets. note that if par ?ds timing preferences in the preference ?e, timing-driven placement and routing is automatically invoked. timing driven par process the isplever software offers timing driven placement and routing through an integrated static timing analysis util- ity (i.e., it does not depend on input stimulus to the circuit). this means that placement and routing is executed according to timing constraints (preferences) that the designer speci?s up front in the design process. par attempts to meet timing constraints in the preference ?e without exceeding the speci?d timing constraints. to use timing-driven par, the designer simply writes timing preferences into a preference (.prf) ?e, which serves as input to the integrated static timing analysis utility. see the process flows section of the isplever on-line help system for more information about the par software and isplever design ?w. general strategy guidelines preferences should be inserted at the front end of a design ?w. this prevents designers from having to change par physical preferences as net names may change with every synthesis run. the tips below are general recommendations. analyze trace results in the integrated static timing analysis utility report (.twr) ?e carefully. look at mapped frequency before you par a design to check for errors and warnings in the preference ?e and to check for logic depth. logic depth is reported in .twr ?es as logic levels (components). determine if design changes are required. a typical example design change is pipelining, or registering, the datapath. this technique may be the only way to achieve high internal frequencies if the designs logic levels are too deep. it is recommended to perform place and route early in the design phase with a preliminary preference ?e to gather information about the design. tune up your preference ?e to include all i/o and internal timing paths as appropriate. the translating board requirements into fpga preferences section of this document goes over an appropriate preference ?e example. establish the pin-out in the preference ?e. locating i/o can also be done in the hdl, as well as in synthesis constraint ?es. push par when necessary by running multiple routing iterations and multiple placement iterations. revise the preference ?e as appropriate, especially utilizing multicycle opportunities when possible. floorplan the design if necessary (see technical note number tn1010, lattice semiconductor design floorplanning ). for lattice semiconductor orca series devices, use clock boosting as a last resort, remembering to run trace hold timing checks on the clock boosted design. refer to the clock boosting section of this document for more information on clock boosting. typical design preferences the full preference language includes many different design constraints from very global preferences to very spe- ci? preferences. to a new user this is a very large list to digest and utilize effectively. listed here are the recom- mended preferences that should be applied to all designs. refer to the constraints & preferences section of the isplever on-line help system for more information on preferences.
lattice semiconductor fpga lattice semiconductor successful place and route 18-3 block asynchronous paths: prevents the timing tools from analyzing any paths from input pads to regis- ters or from input pads to output pads. block ram reads during write: if using pfu based ram, this will prevent timing analysis on a ram read during a write on the same address in a single clock period. frequency/period : each clock net in the design should contain a frequency or period preference. input setup: each synchronous input should have an input_setup preference. clock-to-out: each synchronous output should have a clock_to_out preference. block : all asynchronous reset nets in the design should be blocked. multicycle: the multicycle preference allows the designer to relax a frequency/period constraint on selected paths. proper preferences providing proper preferences is key to a successful design. if the constraints of a preference ?e are tighter than the system requirements, the design will end up being over-constrained. as a consequence, par run times will be con- siderably longer. in addition, over-constraining non-critical paths will force par to waste unnecessary processing power trying to meet these constraints, hence creating possible con?cts with real critical paths that ought to be optimized ?st. on the other hand, if a preference ?e is under-constrained compared to real system requirements, real timing issues not previously seen during dynamic timing simulations and static timing analysis could be observed on a test board, or during production. common causes of over-constrained timing preferences include: multicycle paths not speci?d. multiple paths to/from i/os with different speci?ations. attempt to fool the par tool with tighter than necessary speci?ations. note that over-constrained designs will also need a signi?antly larger amount of processing power and computing resources. as a result, it might be necessary to increase some of the allocated system resources (as in increasing your pc virtual memory paging size). common causes of under-constrained timing preferences include: i/o speci?ations not de?ed. asynchronous logic without maxdelay preferences. internally generated or unintentional clocks not speci?d in preference ?e. blocking critical paths. in general, to make sure that no critical paths were left out due to under-constraining, it is recommended to check for path coverage at the end of a trace report ?e (.twr). an example of such an output is shown in figure 18-1. figure 18-1. trace report (.twr) timing summary example timing summary: --------------- timing errors: 4096 score: 25326584 constraints cover 36575 paths, 6 nets, and 8635 connections (99.0% coverage)
lattice semiconductor fpga lattice semiconductor successful place and route 18-4 this particular example shows a 99.0 % coverage. the way to ?d unconstrained paths is to run trace with the ?heck unconstrained paths checkbox selected. this will give a list of all of the signals that are not covered under timing analysis. in some designs, many of these signals are a common ground net that indeed does not need to be constrained. designers should understand this point and use trace (the isplever static timing analysis tool) to check unconstrained paths to make sure they are not missing any design paths that are timing critical. also, note the timing score shown in figure 18-1. the timing score shows the total amount of error (in picoseconds) for all timing preferences constraining the design. par attempts to minimize the timing score, par does not attempt to maximize frequency. the above discussion can be summarized by the following single equality: quality of preference file = quality of par results translating board requirements into fpga preferences understanding the system board level timing and design constraints is the primary requirement for producing a complete preference ?e. as a result, the major requirements such as clock frequency, i/o timing and loads can be translated into the appropriate preference statements in a constraint ?e. the following exercise will provide an example on how to extract preferences from system conditions. figure 18-2 shows an example system involving the interface between a port controller and a lattice semiconduc- tor fpga. figure 18-2. interface timing example in the system above, several parameters have already been provided: system clock frequency: period (p): 30 ns. port controller maximum output propagation delay (pdmaxp): 18ns. port controller minimum output propagation delay (pdminp): 3 ns. port controller input setup speci?ation (tsp): 5 ns. port controller input hold speci?ation (thp): 3 ns. max board propagation delay (pdmaxb): 6 ns. min board propagation delay (pdminb): 1 ns. port controller to fpga device clock skew and vice versa (tskew): 1 ns. port controller lattice fpga pcb traces 3 ns to 18 ns clk to out, 5 ns setup, 3 ns hold board propagation delay of 1 ns to 2 ns clk 5 pf parasitic board capacitance 9 pf input capacitance, 60 pf ac load 9 pf input capacitance chip to chip clock skew of 1 ns
lattice semiconductor fpga lattice semiconductor successful place and route 18-5 board trace ac loading (cbac): 60 pf. board trace parasitic capacitance (cb): 5 pf. port controller input capacitance (cp) :9 pf. fpga device input capacitance (co): 9 pf. the above information was speci?d under the following environmental conditions: maximum ambient temperature (ta): 70 (c. estimated power consumption (q): 2 w. 680 pbgam package thermal resistance ( j) at 0 feet per minute (fpm) air?w: 13.4 ?/w. the goal of this exercise is to compute the following device i/o constraints: 1. input setup speci?ation. 2. input hold speci?ation. 3. maximum output propagation delay. 4. minimum output propagation delay. 5. output loading. 6. temperature. the only parameter which can be obtained from the above is the device junction temperature: tj = j * q - ta = 13.4 * 2 + 70 = 96.8 ? the required constraints can be computed as follows: 1. input setup speci?ation = p - pdmaxp - pdmaxb - tskew = 30 - 18 - 2 - 1 = 9 ns 2. input hold speci?ation = pdminp + pdminb - tskew = 3 + 1 - 1 = 3 ns 3. output maximum propagation delay requirement = p - tsp - pdmaxb - tskew = 30 - 5 - 6 - 1 = 18 ns 4. output minimum propagation delay requirement = thp - pdminb + tskew = 3 - 1 + 1 = 3 ns 5. output loading = cbac + cb + cp = 60 + 5 + 9 = 74 pf the preference ?e to use for this example is shown in figure 18-3. for more preference language syntax and examples, refer to the constraints & preferences section of the isplever on-line help system.
lattice semiconductor fpga lattice semiconductor successful place and route 18-6 figure 18-3. interface timing preference file example analyzing timing reports this section describes two examples of actual trace reports (.twr report ?e from trace). the purpose is to analyze both examples and understand each section of the reports given the design paths constrained. example 1. multicycle between two different clocks in this ?st example, clka and clkb were assigned 104 mhz and 66 mhz frequencies respectively. in addition, a multicycle constraint was speci?d as per the preference ?e: frequency net "clka" 104 mhz ; frequency net "clkb" 66 mhz ; multicycle "m2" start clknet "clka" end clknet "clkb" 2.000000 x ; see figure 18-4 for the block diagram and waveform for this example. the resulting trace report is shown in figure 18-5. figure 18-4. multicycle clock domains block diagram and waveform period port "clk" 30 ns ; input_setup "port_controller*" 9 ns hold 3 ns clknet "clk"; clock_to_out "port_controller*" 18 ns min 3 ns clknet "clk"; output port "port_controller*" load 74 pf ; temperature 96.8 c ; clk b clka 7.7ns clk a 9.60 ns clkb 7.9 ns 15.15 ns 30.30 ns 7.70 ns 7.90 ns combinational logic
lattice semiconductor fpga lattice semiconductor successful place and route 18-7 figure 18-5. trace report for multicycle clock domains example in figure 18-5, notice how the path is described in terms of ?ogical details. this section shows both the source and destination registers using their unmapped names from the edif (elec- tronic data interchange format) ?e. this is a feature that allows the user to recognize the type of logic being ana- lyzed. based on the declared frequencies for both clocks, we already know the following: clka period = 9.6 ns. clkb period = 15.15 ns. ================================================================================ preference: multicycle "m2" start clknet "clka" end clknet "clkb" 2.000000 x ; 40 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- warning - trce: clock skew between net 'clka' and net 'clkb' not computed: nets may not be related -------------------------------------------------------------------------------- passed: the following path meets requirements by 27.945ns logical details: cell type pin type cell name (clock net +/-) source: ff q v_fifo_bank_1_stfifo0_wr_count_2 (from clka +) destination: ff data in v_fifo_bank_1_stfifo0_wr_count_r_2 (to clkb +) delay: 2.456ns (37.3% logic, 62.7% route), 1 logic levels. constraint details: 2.456ns physical path delay pfu_155 to pfu_156 meets 30.302ns delay constraint less -0.099ns din_set requirement (totaling 30.401ns) by 27.945ns physical path details: name fanout delay (ns) site resource reg_del --- 0.917 r22c16.clk0 to r22c16.q2 pfu_155 (from clka) route 1 1.539 r22c16.q2 to r23c17.din2 v_fifo_bank_1_stfifo0_wr_countz0z_2 (to clkb) -------- 2.456 (37.3% logic, 62.7% route), 1 logic levels. clock skew details: source clock path: name fanout delay (ns) site resource in_del --- 1.192 am17.pad to am17.indd ip_clka route 1 2.989 am17.indd to llppll.clkin ip_clka_c mclk_del --- 0.424 llppll.clkin to llppll.mclk v_io_ppl3_tx4_1_mtppll_rsp_rsppll_0_0 route 177 3.094 llppll.mclk to r22c16.clk0 clka -------- 7.699 (21.0% logic, 79.0% route), 2 logic levels. destination clock path: name fanout delay (ns) site resource in_del --- 1.192 c17.pad to c17.indd ip_clkb route 1 3.091 c17.indd to ulppll.clkin ip_clkb_c mclk_del --- 0.424 ulppll.clkin to ulppll.mclk v_io_ppl3_tx4_1_mtppll_mac_macpll_0_0 route 263 3.182 ulppll.mclk to r23c17.clk0 clkb -------- 7.889 (20.5% logic, 79.5% route), 2 logic levels.
lattice semiconductor fpga lattice semiconductor successful place and route 18-8 no relative phase information exists between both clocks. as a result, trace does not factor in the skews on either clock. as a consequence, we know that, ignoring everything else (clock skews, registers library setups, etc.), a single cycle positive edge to positive edge setup available from clka to clkb is: 15.15ns (refer to waveforms in figure 18-4). hence, with 2x multicycle, the resulting setup would be twice that number, or: ts = 30.3 ns (shows up as delay constraint under constraint details section of trace report) having computed this, the available setup margin is known to be as follows: m = (ts - td) - ds where: td = path delay from clock pin of source register to d pin of destination=2.456 ns. shown in the physical path details section of trace report. ds = destination cell library setup requirement= -0.099 ns. this matches din_set under constraint details section of the .twr trace report. there is no phase relationship between clka and clkb as indicated by the warnings in figure 18-5. hence, the following skews were correctly ignored: tsb = delay or skew on destination clock clkb = 7.889 ns. shown in the clock skews detail section of trace report. tsa = delay or skew on source clock clka = 7.699 ns. shown in the clock skews detail section of trace report. hence: m = (30.3 - 2.46) - (-0.099) = 27.9 ns. this matches the number in the ?assed section at the top of the trace report. example 2. clock_to_out with pll feedback in this example, ip_macclk_c is assigned to 66 mhz and the clock to out propagation delays are constrained in the preference ?e: frequency net "ip_macclk_c" 66 mhz; clock_to_out allports 7.000000 ns clkport "ip_macclk" ; see figure 18-6 for the block diagram for this example. the resulting trace report is shown in figure 18-7.
lattice semiconductor fpga lattice semiconductor successful place and route 18-9 figure 18-6. clock_to_out with pll figure 18-7. trace report for clock_to_out with pll pio ip_macclk rxseln fb clki mclk ulppl cpdel = 8.25 dpdel = 3.17 ns fbdel1 = 3.38 ip_macclk_c fbdel0 = 0.424 ns logic ================================================================================ preference: clock_to_out allports 7.000000 ns clkport "ip_macclk" ; 2 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- passed: the following path meets requirements by 0.681ns logical details: cell type pin type cell name (clock net +/-) source: io-ff out q ppl3_rx5_1_rxselnio (from macclk +) destination: port pad rxseln data path delay: 3.164ns (100.0% logic, 0.0% route), 1 logic levels. clock path delay: 8.249ns (19.6% logic, 80.4% route), 2 logic levels. constraint details: 8.249ns delay ip_macclk to rxseln less 5.094ns feedback compensation 3.164ns delay rxseln to rxseln (totaling 6.319ns) meets 7.000ns offset ip_macclk to rxseln by 0.681ns physical path details: clock path ip_macclk to rxseln: name fanout delay (ns) site resource in_del --- 1.192 c17.pad to c17.indd ip_macclk route 1 3.235 c17.indd to ulppll.clkin ip_macclk_c mclk_del --- 0.424 ulppll.clkin to ulppll.mclk v_io_ppl3_tx4_1/mtppll_mac/macpll_0_0 route 141 3.398 ulppll.mclk to f32.sc macclk -------- 8.249 (19.6% logic, 80.4% route), 2 logic levels. data path rxseln to rxseln: name fanout delay (ns) site resource outregf_de --- 3.164 f32.sc to f32.pad rxseln (from macclk) -------- (100.0% logic, 0.0% route), 1 logic levels. feedback path: name fanout delay (ns) site resource mclk_del --- 0.424 ulppll.clkin to ulppll.mclk v_io_ppl3_tx4_1/mtppll_mac/macpll_0_0 route 141 3.380 ulppll.mclk to ulppll.fb macclk -------- 3.804 (11.1% logic, 88.9% route), 1 logic levels. report: 6.319ns is the minimum offset for this preference.
lattice semiconductor fpga lattice semiconductor successful place and route 18-10 the different path measurements were obtained from the trace report shown in figure 18-7 as follows: dpdel = data path delay = 3.16 ns. shown under physical path details-> data path in the timing report. fbdel0 = feedback cell delay across pll = 0.42 ns, which is the ?st entry value under feedback path. fbdel1 = feedback routing delay from pll output to pll fb pin = 3.38 ns, which is the second entry value under feedback path. the full feedback delay includes both fbdel0 and fbdel1 (0.42 + 3.38 = 3.80) under feedback path, in addition to any internal pll delay added after the fb pin. such a delay is a programmable attribute de?ed as fb_pdel. this programmable value can be set to any of one of 4 values (del0, del1, del2 or del3; del0 being 0 delay) in either the hdl ?e input to synthesis, or in the graphical editor for programmable integrated circuits (epic) soft- ware tool included with the isplever software. therefore, the total feedback delay would be: fbdel = fbdel0 + fbdel1 + fb_pdel = 3.80 + fb_pdel under ?onstraint details of the report ?e, the feedback compensation (fbdel) is shown to be 5.09 ns. since this value is different from 3.804, we conclude that a non-zero value of fb_pdel was applied (5.10 - 3.80 = 1.29 ns). this value corresponds to fb_pdel = del2 in an or4e4-2 device. now, let's verify the available margin on this clock_to_out preference: m = ckout - (cpdel + dpdel - fbdel) = 7.000 - (8.249 + 3.164 - 5.094) = 0.681 ns this value matches the one at the top of the report ?e (?assed section). it also matches the ?al value under ?onstraints details? isplever controlled place and route extensive benchmark experiments have been performed in order to determine the most optimum per device default settings for all par options. at times, improved timing results can be obtained on a design by design basis by trying different variations of the par options. this section describes the techniques that can be used within the isplever graphical user interface (gui) to improve timing results from trace on placed and routed designs. running multiple routing passes improved timing results can be obtained by increasing the number of routing passes during the routing phase of par. the par options window in figure 18-8 can be launched by the following steps: 1. in the project navigator source window, select the target fpga device . 2. in the processes window, right-click the place & route design process and select properties to open the dialog box. in the example screen shot shown in figure 18-8, the router will route the design for ?e routing iterations, or until all the timing preferences are met, whichever comes ?st. for example, par will stop after the second routing itera- tion if it hits a timing score of zero on the second routing iteration. the highest selection in placement effort level will result in longer par run times but may give better design timing results. a lower placement effort will result in shorter par run times but will likely give less than optimal design tim- ing results.
lattice semiconductor fpga lattice semiconductor successful place and route 18-11 figure 18-8. par options window figure 18-9. example par report (.par) file, routing section the place and route (.par) report ?e contains execution information about the par command run. the report also shows the steps taken as the program converges on a placement and routing solution. in the routing convergence example text in figure 18-9, the number in parenthesis is the timing score after each iteration. in this example, tim- ing was met after three routing iterations, as can be seen from the (0) timing score. using multiple placement iterations (cost tables) using multiple placement iterations can be achieved by selecting the advanced options in figure 18-8. as shown in the advanced options of figure 18-8, the number of iterations is set to 10 and the placement start point is set to iteration 1 (cost table 1). only the best ncd ?e is to be saved as per the following line. once par runs, the tool will loop back through the place and route ?w until the number of iterations has reached 10. in this 0 connections routed; 26590 unrouted. starting router resource preassignment completed router resource preassignment. real time: 11 mins 31 secs starting iterative routing. end of iteration 1 26590 successful; 0 unrouted; (151840) real time: 14 mins 29 secs dumping design to file d:\ip\design.ncd. end of iteration 2 26590 successful; 0 unrouted; (577) real time: 16 mins 23 secs dumping design to file d:\ip\design.ncd. end of iteration 3 26590 successful; 0 unrouted; (0) real time: 17 mins 39 secs dumping design to file
lattice semiconductor fpga lattice semiconductor successful place and route 18-12 example, the ncd ?e with the best timing score would be saved. the tool keeps track of the timing and routing per- formance for every iteration in a ?e called the multiple par report (.par). such a ?e is shown in figure 18-10. figure 18-10. multiple par report (.par) figure 18-10 indicates that: the ?_ under the level/cost column means that the placement effort level was set to 5. the placement effort level can range from 1 (lowest) to 5 (highest). 10 different iterations ran (10 cost tables). timing scores are expressed in total picoseconds (ps) by which the design is missing constraints on all preferences. iteration number 4 (cost table 4) achieved a 0 timing score and hence was the design saved. more than one .ncd ?e can be saved. this is user-controlled via the ?lacement save best runs value box shown in figure 18-8. each iteration routed completely. note that, in figure 18-8, if ?lacement iterations (0=run until solved) is set to 0, the tool will run inde?itely through multiple iterations until a 0 timing score is reached. in a design that is known to have large timing viola- tions, a 0 timing score will never be reached. as a consequence, the user must intervene and stop the ?w at a given point in time. in general, multiple placement iterations can help placement but can also use many cpu cycles. multiple place- ment iterations should be used carefully due to system limitations and the uncertainty of results. it is better to ? the root cause of timing problems in the design stage. clock boosting clock boosting, supported in lattice semiconductors orca series device family, is the deliberate introduction of clock skew on a target ?p to increase the setup margin. every programmable ?p-?p in the device has program- mable delay elements before clock inputs for this purpose. the automated clock boosting tool will attempt to meet setup constraints by introducing delays to as many target registers as needed to meet timing, in effect, borrow reg- ister hold margins to meet register set-up timing. the following bullets summarize how clock boosting is accom- plished in lattice semiconductor orca series device family. a 4-tap delay cell structure in front of the clock port of every ?p-?p in the device (includes i/o ?p-?ps) ability to borrow clock cycle time from one easily-met path and give this time to a dif?ult-to-meet path level/ number timing run ncd cost [ncd] unrouted score time status ---------- -------- ------- ----- -------- 5_4 * 0 0 01:58 complete 5_6 0 25 02:01 complete 5_2 0 102 01:45 complete 5_7 0 158 02:15 complete 5_3 0 186 01:54 complete 5_10 0 318 02:39 complete 5_1 0 470 01:51 complete 5_8 0 562 02:25 complete 5_5 0 732 02:00 complete 5_9 0 844 02:27 complete * : design saved.
lattice semiconductor fpga lattice semiconductor successful place and route 18-13 clock boosting is typically most useful in designs that are only missing timing on a few paths for one or two prefer- ences. if the design is missing timing by over a few nanoseconds on any given path, clock boosting will not be able to schedule skew in a way that will eliminate enough timing to make the critical preference. clock boosting run times can be shortened by using a preference ?e with only the failing preferences in it. figure 18-11. clock boosting example the example illustrated in figure 18-11 shows two register-to-register transfers that both need to meet the 10 ns period constraint. by using delay cell del2 to delay the clock input on ?p-?p ff_2, the ?st register transfer will make its period constraint with a new minimum period of ~9.7 ns and the second register transfer will make its period constraint by ~8.3 ns. the d1, d2, and d3 delays shown in figure 18-11 are variable depending on the speed grade and lattice semi- conductor fpga device family. for complete timing information, reference the software generated timing data sheet, included with isplever, for the desired lattice semiconductor fpga device family. to perform clock boosting in the project navigator 1. in the project navigator sources window, select the target device . 2. in the processes window, right-click the clock boosting under place & route design process, and then select properties to open the properties dialog box. 3. select the clock boosting output filename property from the property list and type the name of the out- put ?e name in the edit region (.ncd). 4. click close to close the dialog box. as shown in figure 18-12, the original .ncd and .prf ?es as well as the output .ncd ?e are typed into the corre- sponding entries. checking ?aximize frequency will push the tool to improve the frequency beyond the input preference requirement. this is generally only useful for bench marking. del1 ~= 0.7 ns del2 ~= 1.3 ns del3 ~= 2.0 ns del 1 del 2 del 3 ff_1 clock target performance: 10 ns period (100 mhz) ff_2 ff_3 7 ns 11 ns combinational logic
lattice semiconductor fpga lattice semiconductor successful place and route 18-14 figure 18-12. clock boosting window other important considerations on the practicality of using clock boosting: some circuits show big improvement, others have no gain. clock boosting results are very design-depen- dent. clock boosting uses minimum delay values which have not yet been validated at the system level. automatic clock boosting identi?s skew and hold time issues. however, after clock boosting is performed, designers are strongly recommended to run trace twice, once with regular, maximum delay analysis, and again with minimum delays. the designer should then read over both resultant .twr timing reports to make sure there are no timing errors. the minimum delay analysis is done by checking the ?heck hold times checkbox in the trace options gui window. guided map and par to decrease par runtimes after minor changes to a logical design, guided mapping uses a previously generated .ncd ?e to ?uide the mapping of the new logical design. guided mapping can be performed from the guide file- name property in the project navigator map design process, or speci?d using the command line -g option with the ?e name of the guide ?e. in general, guided map should only be used in conjunction with guided par. to perform guided mapping in the project navigator 1. in the project navigator sources window, select the target device . 2. in the processes window, right-click the map design process, and then select properties to open the properties dialog box. 3. select the guide filename property from the property list and type the name of the guide ?e name in the edit region (.ncd). 4. click close to close the dialog box. the map operation will use the guide ?e to generate the new design ?e. to perform guided par in the project navigator 1. in the project navigator sources window, select the target device . 2. in the processes window, right-click the place & route design process and select properties to open the dialog box. 3. under advanced options, select the guide filename property and type the name of the ?e in the text ?ld.
lattice semiconductor fpga lattice semiconductor successful place and route 18-15 4. click close to close the dialog box. 5. double-click the place & route design process. the isplever software runs the process using the speci?d guide ?e. notes on guided mapping all guidance criteria is based on signal name matching. topology of combinatorial logic is considered when soft- wire luts (swls) exist in the guided ?e. register elements are mapped in two passes. in the ?st pass, register control signals are matched by name exactly. in the second pass, the control signals names are not matched. this methodology provides a greater chance of matching for registers since control signal names have a tendency to change from successive synthesis runs. other matching considerations are as follows: for combinatorial logic, new swls are matched from swls extracted from the guide design. all unmatched logic are mapped through the regular mapping process. the performance of the guided mapped design can be no better than the original. a guide report, .gpr, gives details of the success guided map had in matching with the guide ?e. notes on guided par to decrease par runtimes after minor changes to the physical design ?e (.ncd), guided par uses a previously placed and/or routed .ncd ?e to ?uide the placement and routing of the new .ncd ?e. guided par can be per- formed from the project navigator or speci?d using the command line -g option with the ?e name of the guide ?e. for par to use a guide ?e for design, par ?st tries to ?d a guiding object (i.e., nets, components, and/or macros) in the guide ?e that corresponds to an object in the new .ncd ?e. a guiding object is an object in the guide ?e of the same name, type, and connectivity as an object in the new .ncd ?e. a guided object is an object in the new .ncd ?e that has a corresponding guiding object in the guide ?e. after par compares the objects in each ?e, it places and routes each object of the new .ncd ?e based on the placement/routing of its guiding object. if par fails to ?d a guiding object for a component, for example, par will try to ?d one based on the connectivity. par appends the names of all objects which do not have a guiding object in the guide ?e to .gpr (guided par report) ?e. the matching factor speci?s the percentage of the same connec- tivity that guiding and guided objects must have. it can only be speci?d using the -mf option in the command line. the matching factor option applies to nets and components only. when matching factor is 100 (the default), a guid- ing object must have exactly the same connectivity as the object it is guiding. when a matching factor is speci?d, the value speci?d is taken as the minimum percentage of the same connectivity that a guided object and its guid- ing object have. note that the matching factor is always 100 when the guided par is performed from the project navigator. after all guided objects are placed and routed, par locks down the locations of all guided components and macros and then proceeds with its normal operation. guided par supports the following preferences: use spine, use primary, use secondary, use longline, use halfline, locate comp, locate macro, and hard- placed pgroups. conclusion in general, different designs respond better to different strategies. the processes outlined in this application note may not be optimal for all cases. for a design's ?st place and route, run par at the low placer effort level and with a low number of routing iterations. there is no point in running 100 cost tables if the design's logic depth is too high. the techniques discussed within this document, like interpreting static timing reports and using proper prefer- ences, will guide the user to better par results.
lattice semiconductor fpga lattice semiconductor successful place and route 18-16 technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com
www.latticesemi.com 19-1 tn1071_01.0 june 2004 technical note tn1071 introduction this document describes how to meet board timing requirements for ddr signals. the lattice ddr sdram con- troller ip core, non-pipelined version (ddr-np) is used as an example. figure 19-1 describes the timing diagram for the ddr signals. a total of ?e clocks are used in the ddr board design using the lattice ddr ip core. the following is the clock description: clk : input clock for pll (max. frequency of 133mhz for ddr np) ddr_clk : output clock going to ddr (max. frequency of 133mhz for ddr np) ddr_clk_n : negated version of ddr_clk pll_mclk (clkx) : same as ddr_clk , used inside the fpga only. pll_nclk (clk2x) : a 266mhz clock for ddr np, used inside the fpga only. figure 19-1. ddr signal timing diagram pll clkin clkfb ddr_clk ddr_clk_n clk fpga clkx tree fpga clk2x tree clkx clk2x ddr memory enb q d dqs_out q d ddr_dq d q ddr_dq_in (read flops) ddr_dq_out (write flops) t fpga_clk t cctrl t ddr_clk t cdqs t bdctrl t cdq pll_mclk pll_nclk q d ddr_ad & command signals t bdc t bdds t bdd t pd q d board timing guidelines for the ddr sdram controller ip core
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-2 as shown in figure 19-1, input to pll is clk (133mhz for ddr np). the pll generates pll_mclk (133mhz) and pll_nclk (266mhz). the clocks ddr_clk and ddr_clk_n go to ddr memory and are delayed by i/o pad delay with respect to pll_mclk . the clocks pll_mclk and pll_nclk are internal to the fpga. command and address signals are clocked by a negative edge of pll_mclk . the signal dqs_out acts as a clock for ddr write and is generated by negative edge of pll_nclk . the signal ddr_dq_out is the ddr write data bus and gener- ated by positive edge of pll_nclk . the ?ps ddr_dq_* latch the read data and are clocked by positive edge of pll_nclk . read operation figure 19-2 shows the timing of the ddr read operation. table 19-1 describes the timing arcs of the read opera- tion. figure 19-2. read timing diagram pll_mclk (inside fpga) dq at ddr (min case) dq at ddr (max case ) dq at fpga flops (min case) dq at fpga flops (max case) ddr_clk t ac (max) t ac (max ) t bdd + t pd t bdd + t pd t bdd + t pd t bdd + t pd t skew t skew t ac (min )t ac (min ) at ddr interface inside fpga
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-3 table 19-1. read operation timing arcs set-up time calculation for the data input (max. case) the ddr controller ip core uses the positive edge of pll_nclk to latch in the data. table 19-1 timing arcs are used to calculate the following: max. delay of clock to ddr_dq_in ?ps = t fpga_clk (max) + (t ck * 1/2) - t skew - t fds max. delay of ddr read data to ddr_dq_in ?ps = t ddr_clk (max) + t bdc + t ac (max) + t bdd + t pd to meet set-up time at ddr_dq_in ?ps, clock delay - data delay > 0 therefore: t fpga_clk (max) + (t ck * 1/2) - t skew - t fds - t ddr_clk (max) - t bdc - t ac (max) - t bdd - t pd > 0 isolating the board delays, we get: (t bdd + t bdc ) < t fpga_clk (max) + (t ck * 1/2) - t skew - t fds - t ddr_clk (max) - t ac (max) - t pd (t bdd + t bdc ) < 3.75 - 0.3 - 3.195 - 2.47 + 2.935 - 0.75 - 0.0 (t bdd + t bdc ) < -0.03 ns hold time calculation for the data input (min. case) as shown in figure 19-2, the min data is available at ddr output pins after t ac (min) time from the rising edge of ddr_clk . since t ac (min) is generally a negative number, data appears before the rising edge. this data will incur board delay (t bdd ) and propagation delay from fpga input pad to the ?p-?p input pin (t pd ). min. delay of ddr read data = t ddr_clk (min) + t bdc + t ac (min) + t bdd + t pd symbol description example: ddr-np on orca 4 t ck clock period of ddr_clk 7.5ns t ddr_clk (max) delay from the clk input of the fpga to the ddr_clk pad including feedback com- pensation (clock path delay - feedback path). 2.47 1 t ddr_clk (min) delay from the clk input of the fpga to the ddr_clk pad including feedback com- pensation (clock path delay - feedback path). 1.138 1 t bdc board delay of ddr_clk from fpga to ddr sdram. t ac(max) time from the rising edge of ddr_clk after which the data is available at ddr output pins (max.). 0.75ns t ac(min) time from the rising edge of ddr_clk after which the data is available at ddr output pins (min.). -0.75ns t bdd board delay from ddr sdram data pad to the fpga ddr_dq pad. t pd propagation delay from fpga input pad to the ddr_dq_in ?p-?p input pin (data path delay). 0.0ns 1 t fds set-up time required by the ddr_dq_in ?p-?p ( inreg_set ). 3.195ns 1 t fdh hold time required by the ddr_dq_in ?p-?p ( inreg_hld ). -1.609ns 1 t skew skew of the pll. 0.3ns t fpga_clk (max) delay from the clk input of the fpga to the ddr_dq_in ?p-?p clock input includ- ing feedback compensation (clock out path delay - feedback path). 2.935ns 1 t fpga_clk (min) delay from the clk input of the fpga to the ddr_dq_in ?p-?p clock input includ- ing feedback compensation (clock out path delay - feedback path). 1.239ns 1 1. t fpga_clk, t ddr_clk, t pd and t fds can be easily obtained from the pnr time reports.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-4 min. delay of clock to ddr_dq_in ?ps = t fpga_clk (min) + t skew + t fdh to meet hold time at ddr_dq_in ?ps, data delay - clock delay > 0 therefore: t ddr_clk (min) + t bdc + t ac (min) + t bdd + t pd - t fpga_clk (min) - t skew - t fdh > 0 isolating the board delays, we get: (t bdd + t bdc ) > t fpga_clk (min) + t skew + t fdh - t ddr_clk (min) - t ac (min) - t pd (t bdd + t bdc ) > (1.239) ns + 0.3 + (-1.609ns) - (1.138) - (-0.75) - 0 (t bdd + t bdc ) > -0.458 ns conclusion: to meet read set-up and hold timing, board delay for ddr_dq , ddr_clk and ddr_clk_n should be: -0.458ns < (t bdd + t bdc ) < -0.03ns write operation for a proper write operation, data ( ddr_dq ) should meet set-up (t ds ) and hold (t dh ) time requirements of ddr sdram with respect to ddr_dqs signal. the ddr_dqs signal is generated with respect to negative edge of pll_nclk and data ddr_dq out is generated with respect to positive edge of pll_nclk as shown in figure 19-3. as a result, 1/2 clk2x (3.75ns/2) is provided as set-up and hold for ddr_dq_out with respect to dqs_out . for maximum set-up and hold margin, the ddr_dqs and ddr_dq traces on the board should be matched. table 19-2. write operation timing arcs figure 19-3. write timing diagram write set-up clock delay = t cdqs + 1/2 clk2x - t ds + t bdds data delay = t cdq + t bdd symbol description orca 4 t ds set-up time required by the dq with respect to dqs for ddr sdram. 0.75ns t dh hold time required by the dq with respect to dqs for ddr sdram. 0.75 ns t cdq clock-to-out timing for ddr_dq with respect to pll_nclk . t cdqs clock-to-out timing for ddr_dqs with respect to pll_nclk . t bdds board delay of ddr_dqs from fpga to ddr sdram pins. pll_nclk (clk2x) dqs_out ddr_dq_out t cdqs t cdq
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-5 clock delay - data delay > 0 therefore: t cdqs + 1/2 clk2x - t ds + t bdds - t cdq - t bdd > 0 assumptions for write set-up and hold equations: 1. t bdds and t bdd are equal (board delays are same both for dqs_out and ddr_dq_out ). 2. t cdq and t cdqs are equal (both are output delays from i/o ?p). therefore: 1/2 clk2x - t ds > 0 3.75/2 - 0.75 > 0 1.125 > 0 write hold data delay = t cdq + t bdd clock delay = t cdqs + 1/2 clk2x + t dh + t bdds data delay - clock delay > 0 therefore: t cdqs + 1/2 clk2x - t dh + t bdds - t cdq - t bdd > 0 assumptions for write set-up and hold equations: 1. t bdds and t bdd are equal (board delays are same both for dqs_out and ddr_dq_out ). 2. t cdq and t cdqs are equal (both are output delays from i/o ?p). therefore: 1/2 clk2x - t dh > 0 3.75/2 - 0.75 > 0 1.125 > 0 address and command signals address ( ddr_ad ) and command signals ( ddr_cas , ddr_ras , ddr_we ) should meet set-up (t ds ) and hold (t dh ) timings at ddr interface with respect to positive edge of ddr_clk . address and command signals are clocked using negative edge of pll_mclk inside the fpga as shown below. the ddr_clk signal is a delayed by pad delay and board delay at ddr interface compared to pll_mclk inside the fpga. as a result, 1/2 clkx of set-up and hold is provided by design.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-6 table 19-3. timing arcs for address and command signals figure 19-4. timing diagram for address and command signals set-up calculation max delay of clock to ddr = t ddr_clk (max) + t bdc + t ck * 1/2 - t skew - t ds max delays of command signals data to ddr = t cctrl (max) + t bdctrl to meet set up time at ddr memory, clock delay - data delay > 0 therefore: t ddr_clk (max) + t bdc + t ck * 1/2 - t skew - t ds - t cctrl (max) - t bdctrl > 0 isolating the board delays, we get: t bdctrl - t bdc < t ddr_clk (max) + t ck * 1/2 - t skew - t ds - t cctrl (max) t bdctrl - t bdc < 2.47 + 3.75 - 0.3 - 0.75 - 4.834 t bdctrl - t bdc < 0.336 ns symbol description orca4 t cctrl (max) is the clock-to-out time for ddr_ad and command signals. (clock path delay - feedback path) + data path delay 4.834 ns t cctrl (min) is the clock-to-out time for ddr_ad and command signals. (clock path delay - feedback path) + data path delay 2.147 ns t bdctrl is the board delay of ddr_ad and command signals from fpga pins to ddr sdram pins. pll_mclk (clkx) ddr_ad, command_signals t cctrl at fpga at ddr interface ddr_clk t ddr_clk + t bdc ddr_ad, command_signals t bdctrl t skew t skew t ds t dh clk
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-7 hold calculation min delay of command signals data to ddr = t cctrl (min) + t bdctrl + t ck * 1/2 min delay of clock to ddr = t ddr_clk (min) + t bdc + t skew + t dh to meet hold time at ddr memory, data delay - clock delay > 0 therefore: t cctrl (min) + t bdctrl + t ck * 1/2 - t ddr_clk (min) - t bdc - t skew - t dh > 0 isolating the board delays, we get: t bdctrl - t bdc > - t cctrl (min) - t ck * 1/2 + t ddr_clk (min) + t skew + t dh t bdctrl - t bdc > -2.147 - 3.75 + (1.138) + 0.3 + 0.75 t bdctrl - t bdc > -3.709 t bdctrl - t bdc > -3.709 ns conclusion: to meet set-up and hold timings of command signals, board delay of command signals ddr_clk and ddr_clk_n should be: -3.709 ns < (t bdctrl - t bdc ) < 0.336 ns board design guidelines the ddr_clk and ddr_clk_n pads should be placed adjacent to each other in the fpga to get similar internal fpga delays. the ddr_clk and ddr_clk_n trace delays on the board should be matched. the dq trace delays can be calculated using the following formula, for memory reads: t skew + t fdh - t ac (min) - t pd - t ddr_clk + t fpga_clk < (t bdd + t bdc ) < (t ck * 1/2) - t skew - t fds - t ac (max) - t pd - t ddr_clk + t fpga_clk the dq and dqs trace lengths should be balanced and matching to get maximum set-up/hold time during memory writes. the address and control signals for the ddr sdram are generated on the negative edge of the fpga clock. the trace lengths for address and control lines are calculated using following equation: -t cctrl - t ck * 1/2 + t ddr_clk + t skew + t dh < (t bdctrl - t bdc ) < t ddr_clk + t ck * 1/2 - t skew - t ds - t cctrl + t bdc as shown in figure 19-1, both fpga internal clock and ddr_clk are generated by a single pll. it may be dif?ult to meet read data set-up and hold timing with a single pll. as shown in figure 19-5, a two-pll clocking scheme is proposed to meet read data set-up and hold timing. adjusting feedback delay of pll2 can control delay of pll_mclk . increasing delay on pll_mclk can increase the read set-up margin but it also decreases the hold margin. to get better timing, skew between ddr_clk and pll_mclk has to be minimized.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-8 figure 19-5. two pll clocking scheme technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com ddrct_np ip core ppll div3 div2 div0 div1 hppll n-stage tbufs ddr_clk (133mhz) ddr_clk_n (133mhz) sysclock 133mhz clkin mclk fb nclk div3 div2 div0 div1 clkin mclk fb nclk pll1 pll2 pll_nclk (266mhz) pll_mclk (133mhz) pll1_nclk (133mhz) pio pio user interface ddr sdram memory
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-9 appendix a. example extractions of delays from timing reports from the set-up report below, which was run for max conditions: ? pd = 0.0 ns ? fds = 3.195 ns ? fpga_clk (max) = 6.206 - 3.271 = 2.935 ns =============================================================== preference: input_setup port ?ddr_dq_*? 2.000000 ns clknet ?pll_nclk? ; 32 items scored, 0 timing errors detected. ---------------------------------------------------------------------------------------------------- ----------------------------- passed: the following path meets requirements by 1.740ns logical details: cell type pin type cell name (clock net +/-) source: port pad ddr_dq_23 destination: o-ff in data in u1_ddrct_np_o4_1_008/u3_databusif/ddr_dqoez0z_23 (to pll_nclk +) data path delay: 0.000ns (0.0% logic, 0.0% route), 0 logic levels. clock path delay: 6.206ns (29.3% logic, 70.7% route), 2 logic levels. constraint details: 0.000ns delay ddr_dq_23 to ddr_dq_23 less 2.000ns offset ddr_dq_23 to clk (totaling -2.000ns) meets 6.206ns delay clk to ddr_dq_23 less 3.271ns feedback compensation less 3.195ns inreg_set requirement (totaling -0.260ns) by 1.740ns physical path details: data path ddr_dq_23 to ddr_dq_23: name fanout delay (ns) site resource -------- 0.000 (0.0% logic, 0.0% route), 0 logic levels. clock path clk to ddr_dq_23: name fanout delay (ns) site resource in_del --- 1.431 ab4.pad to ab4.inck clk route 1 0.816 ab4.inck to llhppll.clkin clk_c nclk_del --- 0.385 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 3.574 llhppll.nclk to n24.sc pll_nclk -------- 6.206 (29.3% logic, 70.7% route), 2 logic levels.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-10 feedback path: name fanout delay (ns) site resource nclk_del --- 0.385 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 2.886 llhppll.nclk to llhppll.fb pll_nclk -------- 3.271 (11.8% logic, 88.2% route), 1 logic levels. report: 0.260ns is the minimum offset for this preference. from the hold report below, which was run for min conditions: t pd = 0.0 ns t fdh = -1.609 ns t fpga_clk (min) = 3.144 - 1.905 = 1.239 ns =============================================================== preference: input_setup port ?ddr_dq_*? 2.000000 ns clknet ?pll_nclk? ; 32 items scored, 0 timing errors detected. ---------------------------------------------------------------------------------------------------- -------- passed: the following path meets requirements by 0.370ns logical details: cell type pin type cell name (clock net +/-) source: port pad ddr_dq_31 destination: io-ff in data in u1_ddrct_np_o4_1_008/u3_databusif/ddr_dqoez0z_31 (to pll_nclk +) data path delay: 0.000ns (0.0% logic, 0.0% route), 0 logic levels. clock path delay: 3.144ns (25.7% logic, 74.3% route), 2 logic levels. constraint details: 0.000ns delay ddr_dq_31 to ddr_dq_31 plus 0.000ns hold offset ddr_dq_31 to clk (totaling 0.000ns) meets 3.144ns delay clk to ddr_dq_31 plus 1.905ns feedback compensation less -1.609ns inreg_hld requirement (totaling -0.370ns) by 0.370ns physical path details: data path ddr_dq_31 to ddr_dq_31: name fanout delay (ns) site resource -------- 0.000 (0.0% logic, 0.0% route), 0 logic levels.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-11 clock path clk to ddr_dq_31: name fanout delay (ns) site resource in_del --- 0.576 ab4.pad to ab4.inck clk route 1 0.507 ab4.inck to llhppll.clkin clk_c nclk_del --- 0.231 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 1.830 llhppll.nclk to c25.sc pll_nclk -------- 3.144 (25.7% logic, 74.3% route), 2 logic levels. feedback path: name fanout delay (ns) site resource nclk_del --- 0.231 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 1.674 llhppll.nclk to llhppll.fb pll_nclk -------- 1.905 (12.1% logic, 87.9% route), 1 logic levels. report: there is no minimum offset greater than zero for this preference. from the set-up report below, which was run for max conditions: t ddr_clk (max) = 5.741 - 3.271 = 2.47 ns =========================================================================== preference: clock_to_out port ?ddr_cas_n? max 5.500000 ns clkport ?clk? clkout port ?ddr_clk? ; 1 item scored, 0 timing errors detected. ---------------------------------------------------------------------------------------------------- ----------------------------- passed: the following path meets requirements by 3.182ns logical details: cell type pin type cell name (clock net +/-) source: unknown q u1_ddrct_np_o4_1_008/u1_cmdexe/ddr_cas_nz0 (from ddr_clk_c -) destination: port pad ddr_cas_n data path delay: 1.713ns (100.0% logic, 0.0% route), 1 logic levels. clock path delay: 6.346ns (28.6% logic, 71.4% route), 2 logic levels. constraint details: 6.346ns delay clk to ddr_cas_n less 3.271ns feedback compensation 1.713ns delay ddr_cas_n to ddr_cas_n less 2.470ns delay clk to ddr_clk (totaling 2.318ns) meets 5.500ns offset clk to ddr_cas_n by 3.182ns physical path details: clock path clk to ddr_cas_n: name fanout delay (ns) site resource
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-12 in_del --- 1.431 ab4.pad to ab4.inck clk route 1 0.816 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.385 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 3.714 llhppll.mclk to ae15.sc ddr_clk_c -------- 6.346 (28.6% logic, 71.4% route), 2 logic levels. data path ddr_cas_n to ddr_cas_n: name fanout delay (ns) site resource outreg_del --- 1.713 ae15.sc to ae15.pad ddr_cas_n (from ddr_clk_c) -------- 1.713 (100.0% logic, 0.0% route), 1 logic levels. clock out path: name fanout delay (ns) site resource in_del --- 1.431 ab4.pad to ab4.inck clk route 1 0.816 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.385 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 1.191 llhppll.mclk to af3.outdd ddr_clk_c outdd_del --- 1.918 af3.outdd to af3.pad ddr_clk -------- 5.741 (65.0% logic, 35.0% route), 3 logic levels. feedback path: name fanout delay (ns) site resource nclk_del --- 0.385 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 2.886 llhppll.nclk to llhppll.fb pll_nclk -------- 3.271 (11.8% logic, 88.2% route), 1 logic levels. report: 2.318ns is the minimum offset for this preference. from the hold report below, which was run for min conditions: t ddr_clk (min) = 3.043 - 1.905 = 1.138 ns =========================================================================== preference: clock_to_out port ?ddr_cas_n? max 5.500000 ns clkport ?clk? clkout port ?ddr_clk? ; 1 item scored, 0 timing errors detected. ---------------------------------------------------------------------------------------------------- ----------------------------- passed: the following path meets requirements by 1.056ns logical details: cell type pin type cell name (clock net +/-) source: unknown q u1_ddrct_np_o4_1_008/u1_cmdexe/ddr_cas_nz0 (from ddr_clk_c -) destination: port pad ddr_cas_n data path delay: 0.928ns (100.0% logic, 0.0% route), 1 logic levels.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-13 clock path delay: 3.171ns (25.4% logic, 74.6% route), 2 logic levels. constraint details: 3.171ns delay clk to ddr_cas_n less 1.905ns feedback compensation 0.928ns delay ddr_cas_n to ddr_cas_n less 1.138ns delay clk to ddr_clk (totaling 1.056ns) meets 0.000ns hold offset clk to ddr_cas_n by 1.056ns physical path details: clock path clk to ddr_cas_n: name fanout delay (ns) site resource in_del --- 0.576 ab4.pad to ab4.inck clk route 1 0.507 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.231 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 1.857 llhppll.mclk to ae15.sc ddr_clk_c -------- 3.171 (25.4% logic, 74.6% route), 2 logic levels. data path ddr_cas_n to ddr_cas_n: name fanout delay (ns) site resource outreg_del --- 0.928 ae15.sc to ae15.pad ddr_cas_n (from ddr_clk_c) -------- 0.928 (100.0% logic, 0.0% route), 1 logic levels. clock out path: name fanout delay (ns) site resource in_del --- 0.576 ab4.pad to ab4.inck clk route 1 0.507 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.231 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 0.778 llhppll.mclk to af3.outdd ddr_clk_c outdd_del --- 0.951 af3.outdd to af3.pad ddr_clk -------- 3.043 (57.8% logic, 42.2% route), 3 logic levels. feedback path: name fanout delay (ns) site resource nclk_del --- 0.231 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 1.674 llhppll.nclk to llhppll.fb pll_nclk -------- 1.905 (12.1% logic, 87.9% route), 1 logic levels. report: 1.056ns is the maximum offset for this preference. ===========================================================================
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-14 from the set-up report below, which was run for max conditions. the report shown here is for ddr_ad. t cctrl (max) = (6.392-3.271) + 1.713 = 4.834 ns find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. then take the max of those delays as t cctrl (max). ============================================================================================ preference: clock_to_out port ?ddr_ad_*? 5.500000 ns clknet ?ddr_clk_c? ; 12 items scored, 0 timing errors detected. passed: the following path meets requirements by 0.666ns logical details: cell type pin type cell name (clock net +/-) source: unknown q u1_ddrct_np_o4_1_008/u1_cmdexe/ddr_adz0z_6 (from ddr_clk_c -) destination: port pad ddr_ad_6 data path delay: 1.713ns (100.0% logic, 0.0% route), 1 logic levels. clock path delay: 6.392ns (28.4% logic, 71.6% route), 2 logic levels. constraint details: 6.392ns delay clk to ddr_ad_6 less 3.271ns feedback compensation 1.713ns delay ddr_ad_6 to ddr_ad_6 (totaling 4.834ns) meets 5.500ns offset clk to ddr_ad_6 by 0.666ns physical path details: clock path clk to ddr_ad_6: name fanout delay (ns) site resource in_del --- 1.431 ab4.pad to ab4.inck clk route 1 0.816 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.385 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 3.760 llhppll.mclk to ae14.sc ddr_clk_c -------- 6.392 (28.4% logic, 71.6% route), 2 logic levels. data path ddr_ad_6 to ddr_ad_6: name fanout delay (ns) site resource outreg_del --- 1.713 ae14.sc to ae14.pad ddr_ad_6 (from ddr_clk_c) -------- 1.713 (100.0% logic, 0.0% route), 1 logic levels. feedback path: name fanout delay (ns) site resource nclk_del --- 0.385 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 2.886 llhppll.nclk to llhppll.fb pll_nclk -------- 3.271 (11.8% logic, 88.2% route), 1 logic levels. report: 4.834ns is the minimum offset for this preference.
board timing guidelines lattice semiconductor for the ddr sdram controller ip core 19-15 from the hold report below, which was run for min conditions. the report shown here is for ddr_ad* only. t cctrl (min) = (3.124-1.905) + 0.928 = 2.147 ns find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. then take the min of those delays as t cctrl (min). =========================================================================== preference: clock_to_out port ?ddr_ad_*? 5.500000 ns clknet ?ddr_clk_c? ; 12 items scored, 0 timing errors detected. passed: the following path meets requirements by 2.147ns logical details: cell type pin type cell name (clock net +/-) source: unknown q u1_ddrct_np_o4_1_008/u1_cmdexe/ddr_adz0z_4 (from ddr_clk_c -) destination: port pad ddr_ad_4 data path delay: 0.928ns (100.0% logic, 0.0% route), 1 logic levels. clock path delay: 3.124ns (25.8% logic, 74.2% route), 2 logic levels. constraint details: 3.124ns delay clk to ddr_ad_4 less 1.905ns feedback compensation 0.928ns delay ddr_ad_4 to ddr_ad_4 (totaling 2.147ns) meets 0.000ns hold offset clk to ddr_ad_4 by 2.147ns physical path details: clock path clk to ddr_ad_4: name fanout delay (ns) site resource in_del --- 0.576 ab4.pad to ab4.inck clk route 1 0.507 ab4.inck to llhppll.clkin clk_c mclk_del --- 0.231 llhppll.clkin to llhppll.mclk u2_ddr_pll_orca/ddr_pll_0_0 route 449 1.810 llhppll.mclk to t26.sc ddr_clk_c -------- 3.124 (25.8% logic, 74.2% route), 2 logic levels. data path ddr_ad_4 to ddr_ad_4: name fanout delay (ns) site resource outreg_del --- 0.928 t26.sc to t26.pad ddr_ad_4 (from ddr_clk_c) -------- 0.928 (100.0% logic, 0.0% route), 1 logic levels. feedback path: name fanout delay (ns) site resource nclk_del --- 0.231 llhppll.clkin to llhppll.nclk u2_ddr_pll_orca/ddr_pll_0_0 route 136 1.674 llhppll.nclk to llhppll.fb pll_nclk -------- 1.905 (12.1% logic, 87.9% route), 1 logic levels. report: 2.220ns is the maximum offset for this preference.
?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 20-1 tn1074_01.3 september 2006 technical note tn1074 introduction as ball grid array (bga) packages become increasingly popular, it is important to understand how they are affected by various board layout techniques. this document provides a brief overview of pcb layout considerations when working with bga packages. it outlines some of the most common problems and provides tips for avoiding them at the design stage. advantages and disadvantages of bga packaging one of the greatest advantages of bga packaging over other new technologies is that it can be supported with existing placement and assembly equipment. bgas also offer signi?antly more misalignment tolerance, less sus- ceptibility to coplanarity issues and easier pcb signal routing under a bga package (see figure 20-1). the primary drawback of bga packaging is the inability to access the solder joints for testing and inspection (a later section in this document provides layout recommendations for testing). at best, only the outermost row of balls can be seen, and board size and other components often restrict even that view. the best option available for a complete inspection of the device is x-ray imaging. by this means, the user can visually assess shorted connec- tions, missing balls, ?led vias, and in some cases, opens (see figure 20-2). opens and partial opens (where the solder did not wet the entire pad) are more dif?ult to see and may require higher resolution equipment. figure 20-1. misalignment of bga balls vs. qfp leads bga ball qfp leads qfp leads 0.24 0.24 0.12 0.12 bga ball solderable pad solderable pad pcb layout recommendations for bga packages
pcb layout recommendations lattice semiconductor for bga packages 20-2 figure 20-2. example of how defects may appear in an x-ray image pcb layout all lattice bga packages utilize solder mask de?ed (smd) pads. for optimized solder joint formation, the pcb pads should match the bga solder pads (see figure 20-3). for example, if the bga has solder pads with 0.60 mm openings, so should the corresponding site on the pcb. figure 20-3. smd pad with example dimensions plated through hole (via) placement probably the most critical aspect of bga pcb layout is the consideration for plated through hole (pth) place- ment. if the pad is too close or on top of the hole, or if there is no solder mask covering the via, then it is possible for the ball solder and paste to melt and be wicked into the hole. if enough solder is lost into the hole, the result could be an open for that lead. while this type of defect can usually be detected in an x-ray image, it is best avoided at layout (see figure 20-2). normal solder joint via missing solder ball solder-filled via solder short e m l via land solder land solder mask over land via cross section opening in solder mask
pcb layout recommendations lattice semiconductor for bga packages 20-3 bga board layout recommendations bga package types further information for additional information, please visit the web sites listed below. www .amk or .com/products/all_products www .latticesemi.com/lit/docs/pac kage/amk or_bga_appnote .pdf technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history pitch 0.5mm csbga pitch 0.8mm cabga pitch 1.00mm (fpbga, ftbga, fpsbga, fcbga) pitch 1.27mm pbga, sbga all other fpbga, ftbga, fpsbga 100 fpbga, 256 ftbga organic fcbga ceramic fcbga solder land diameter (l) 0.43 0.53 0.66 0.53 0.80 0.70 0.80 opening in solder mask (m) 0.30 0.40 0.45 0.40 0.60 0.50 0.63 solder ball land pitch (e) 0.50 0.80 1.00 1.00 1.00 1.00 1.27 note: the numbers in this table are intended to be used as an example only. the actual numbers are dependent on the pcb manufac turing tol- erance. package type description pbga plastic bga with 1.27 mm solder ball pitch. die up con?uration. fpbga fine pitch bga ?plastic bga with 1.0 mm solder ball pitch. die up con?uration. ftbga fine pitch thin bga ?thin plastic bga with 1.0 mm solder ball pitch. die up con?uration. cabga chip array bga ?plastic bga with 0.8 mm solder ball pitch. die up con?uration. csbga chip scale bga ?plastic bga with 0.5 mm solder ball pitch. die up con?uration. fcbga flip-chip bga with 1.0 mm solder ball pitch. die down con?uration. may have a ceramic or plastic sub- strate. sbga super bga ?similar to pbga, but with an integrated heatsink plate. this package has 1.27 mm solder ball pitch and die down con?uration. sbga packages offer enhanced thermal dissipation capability. fpsbga fine pitch sbga ?super bga with 1.0 mm solder ball pitch. die down con?uration. date version change summary january 2005 01.0 initial release. november 2005 01.1 figures updated. june 2006 01.2 removed nsmd content. september 2006 01.3 added note to bga board layout recommendations table. reformatted bga package types section in tabular format.
section iii. latticexp family handbook revision history
april 2007 handbook hb1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 20-1 revision history date handbook revison number change summary february 2005 01.0 initial release. april 2005 01.1 latticexp family data sheet updated to version 01.1. technical note tn1051 updated to version 01.1. may 2005 01.2 latticexp family data sheet updated to version 01.2. july 2005 01.3 latticexp family data sheet updated to version 02.0. technical note tn1052 updated to version 02.1. july 2005 01.4 latticexp family data sheet updated to version 02.1. technical note tn1056 updated to version 03.1. august 2005 01.5 latticexp family data sheet updated to version 02.2. september 2005 01.6 latticexp family data sheet updated to version 03.0. september 2005 01.7 october 2005 01.8 latticexp family data sheet updated to version 03.1. technical note tn1056 updated to version 03.2. technical note tn1051 updated to version 01.5. technical note tn1050 updated to version 03.1. technical note tn1049 updated to version 04.0. technical note tn1082 updated to version 01.3. technical note tn1054 updated to version 01.1. technical note tn1008 updated to version 02.1. technical note tn1074 updated to version 01.1. december 2005 02.0 latticexp family data sheet updated to version 04.0. february 2006 02.1 latticexp family data sheet updated to version 04.1. technical note tn1051 updated to version 01.6. technical note tn1082 updated to version 01.4. technical note tn1054 updated to version 01.2. march 2006 02.2 latticexp family data sheet updated to version 04.2. march 2006 02.3 latticexp family data sheet updated to version 04.3. technical note tn1056 updated to version 03.3. april 2006 02.4 latticexp family data sheet updated to version 04.4. may 2006 02.5 latticexp family data sheet updated to version 04.5. technical note tn1051 updated to version 01.7. october 2006 02.6 latticexp family data sheet updated to version 04.7. technical note tn1074 updated to version 01.3. technical note tn1051 updated to version 01.8. technical note tn1049 updated to version 04.1. december 2006 02.7 latticexp family data sheet updated to version 04.8. technical note tn1052 updated to version 02.2. february 2007 02.8 latticexp family data sheet updated to version 04.9. latticexp family handbook revision history
20-2 revision history lattice semiconductor latticexp family handbook april 2007 02.9 technical note tn1050 updated to version 03.2. note: for detailed revision changes, please refer to the revision history for each document. date handbook revison number change summary


▲Up To Search▲   

 
Price & Availability of LFXP10E-4F484C

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X